AREA SELECTIVE CYCLIC DEPOSITION FOR VFET TOP SPACER

• US 20200135893A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BI, ZHENXING, Cheng, Kangguo, Xu, YONGAN, Song, Yi
• Granted Patent: US 10,749,011 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a first semiconductor fin over a substrate;

forming a second semiconductor fin over the substrate and adjacent to the first semiconductor fin;

forming a dielectric isolation region between the first semiconductor fin and the second semiconductor fin; and

forming a top spacer between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region;

wherein the dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin.

2. The method of claim 1 further comprising forming a conductive gate over a channel region of the first semiconductor fin and over a channel region of the second semiconductor fin.

3. The method of claim 2 further comprising recessing the conductive gate below a top surface of the first semiconductor fin to expose a surface of the dielectric isolation region.

4. The method of claim 1, wherein cyclically depositing dielectric layers over the dielectric isolation region comprises:

forming a first cyclic dielectric layer over a surface of the dielectric isolation region;

forming a second cyclic dielectric layer over the first cyclic dielectric layer; and

forming a third cyclic dielectric layer over the second cyclic dielectric layer.

5. The method of claim 4, wherein the first cyclic dielectric layer, the second cyclic dielectric layer, and the third cyclic dielectric layer comprise a same dielectric material.

6. The method of claim 4, wherein the first cyclic dielectric layer comprises a first dielectric material and the second cyclic dielectric layer comprises a second dielectric material.

7. The method of claim 6, wherein the first cyclic dielectric layer comprises SiN and the second cyclic dielectric layer comprises SiBCN or SiOCN.

8. The method of claim 1 further comprising planarizing the top spacer to a top surface of the first semiconductor fin.

9. The method of claim 8, wherein planarizing the top spacer comprises applying to the top spacer an isotropic nitride selective etch.

10. A method for forming a semiconductor device, the method comprising:

forming a first semiconductor fin over a substrate;

forming a second semiconductor fin over the substrate and adjacent to the first semiconductor fin;

forming a conductive gate over a channel region of the first semiconductor fin and over a channel region of the second semiconductor fin;

forming a dielectric isolation region between the first semiconductor fin and the second semiconductor fin, the dielectric isolation region between opposite sidewalls of the conductive gate; and

selectively depositing a dielectric material on a surface of the dielectric isolation region.

11. The method of claim 10, wherein the dielectric material is inhibited from depositing on a surface of the first semiconductor fin, a surface of the second semiconductor fin, and a surface of the conductive gate.

12. The method of claim 10 further comprising forming a top source or drain (S/D) region on a surface of the first semiconductor fin.

13. The method of claim 12 further comprising forming a contact over the top S/D region.

14. The method of claim 10 further comprising forming a bottom source or drain (S/D) region on a surface of the substrate, a portion of the bottom S/D region in contact with a sidewall of the first semiconductor fin.

15. The method of claim 14 further comprising forming a bottom spacer on a surface of the bottom S/D region.

16. A semiconductor device comprising:

a first semiconductor fin over a substrate;

a second semiconductor fin over the substrate and adjacent to the first semiconductor fin;

a dielectric isolation region between the first semiconductor fin and the second semiconductor fin; and

a top spacer between the first semiconductor fin and the second semiconductor fin, the top spacer comprising cyclically deposited dielectric layers.

17. The semiconductor device of claim 16 further comprising a conductive gate over a channel region of the first semiconductor fin and over a channel region of the second semiconductor fin.

18. The semiconductor device of claim 16, wherein the top spacer comprises a first cyclic dielectric layer, a second cyclic dielectric layer, and a third cyclic dielectric layer.

19. The semiconductor device of claim 18, wherein the first cyclic dielectric layer comprises a first dielectric material and the second cyclic dielectric layer comprises a second dielectric material.

20. The semiconductor device of claim 19, wherein the first cyclic dielectric layer comprises SiN and the second cyclic dielectric layer comprises SiBCN or SiOCN.