Forming Epitaxial Structures in Fin Field Effect Transistors

• US 20200135894A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 02/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chan, Chia-Ling, Chen, Derek, Chen, Liang-Yin, Kuo, Chien-I
• Granted Patent: US 11,495,674 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Claims

1. A semiconductor device, comprising:

a fin over a substrate;

a gate structure over the fin; and

an epitaxial source/drain feature over the fin and adjacent to the gate structure, wherein the epitaxial source/drain feature includes a first layer, a second layer over the first layer, and a third layer over the second layer, wherein the second layer is doped with a first dopant, and wherein the third layer is doped with a second dopant having a greater atomic weight than the first dopant.

2. The semiconductor device of claim 1, wherein the first layer is doped with the first dopant.

3. The semiconductor device of claim 1, wherein the first layer is doped with the second dopant.

4. The semiconductor device of claim 1, wherein the first layer separates the second layer from the fin.

5. The semiconductor device of claim 4, wherein a diffusion distance of the first dopant in the second layer is less than a thickness of the first layer.

6. The semiconductor device of claim 1, wherein the first dopant is boron and the second dopant is carbon.

7. The semiconductor device of claim 1, wherein the first dopant is phosphorous and the second dopant is arsenic.

8. A semiconductor device, comprising:

a semiconductor layer disposed over a substrate;

a metal gate stack disposed over a channel region of the semiconductor layer; and

an source/drain feature disposed in the semiconductor layer and adjacent to the metal gate stack, wherein the source/drain feature includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer, wherein the second epitaxial layer is doped with a first dopant, wherein the third epitaxial layer is doped with a second dopant different from the first dopant, the first dopant and the second dopant being of n-conductivity type.

9. The semiconductor device of claim 8, wherein the second dopant has a higher atomic number than the first dopant.

10. The semiconductor device of claim 8, wherein the first epitaxial layer is doped with either the first dopant or the second dopant.

11. The semiconductor device of claim 10, wherein the second epitaxial layer is doped with the first dopant at a first concentration, and wherein the first epitaxial layer is doped with the first dopant at a second concentration lower than the first concentration.

12. The semiconductor device of claim 8, wherein the first epitaxial layer is configured to be U-shaped.

13. The semiconductor device of claim 8, wherein the first epitaxial layer is embedded in a top portion of the semiconductor layer.

14. The semiconductor device of claim 8, wherein the first dopant is phosphorous and the second dopant is arsenic.

15. A device, comprising:

a fin over a semiconductor substrate;

a gate structure over the fin; and

an epitaxial source/drain feature over the fin and adjacent to the gate structure, wherein the epitaxial source/drain feature includes a first layer, a second layer surrounded by the first layer, and a third layer over the second layer, wherein the first layer is doped with a first dopant at a first concentration, wherein the second layer is doped with the first dopant at a second concentration higher than the first concentration, and wherein the third layer is doped with a second dopant having a higher atomic weight than the first dopant, the first dopant and the second dopant being of the same conductivity type.

16. The device of claim 15, wherein the first layer physically separates the second layer from the fin.

17. The device of claim 16, wherein a separation distance between the second layer and the fin is between about 2 nanometers and about 10 nanometers.

18. The device of claim 15, wherein the third layer contacts both the first and the second layers.

19. The device of claim 15, wherein the first dopant and the second dopant are both of n-conductivity type, wherein the first dopant is phosphorous, and wherein the second dopant is arsenic.

20. The device of claim 15, wherein the first dopant and the second dopant are both of p-conductivity type, wherein the first dopant is boron, and wherein the second dopant is carbon.