NOVEL EPI SEMICONDUCTOR MATERIAL STRUCTURES IN SOURCE/DRAIN REGIONS OF A TRANSISTOR DEVICE FORMED ON AN SOI SUBSTRATE

• US 20200135895A1
• Filed: 12/26/2019
• Published: 04/30/2020
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Pandey, Shesh Mani, Singh, Jagar, Holt, Judson R.
• Granted Patent: US 11,049,955 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.

Claims

1. A transistor formed above a semiconductor-on-insulator (SOI) substrate comprising a bulk semiconductor layer, a buried insulation layer positioned on said bulk semiconductor layer and an active semiconductor layer positioned on said buried insulation layer, said transistor comprising:

a gate structure, a sidewall spacer and source/drain regions;

openings extending through said active semiconductor layer of said SOI substrate in said source/drain regions adjacent said sidewall spacer;

recesses in said buried insulation layer of said SOI substrate in said source/drain regions of said transistor, wherein said recesses extend laterally under a portion of said active semiconductor layer; and

an epi semiconductor material positioned in at least said recesses in said buried insulation layer, wherein a portion of said buried insulation layer is positioned between said epi semiconductor material positioned in at least said recesses and said bulk semiconductor layer of said SOI substrate.

2. The transistor of claim 1, wherein said epi semiconductor material is substantially un-doped.

3. The transistor of claim 1, wherein said epi semiconductor material comprises a first substantially un-doped epi semiconductor material that is positioned at least partially within said recesses and a second doped epi semiconductor material that is positioned above said first substantially un-doped epi semiconductor material in said source/drain regions.

4. The transistor of claim 3, wherein said first substantially un-doped epi semiconductor material and said second doped epi semiconductor material are comprised of different semiconductor materials.

5. The transistor of claim 3, wherein said first substantially un-doped epi semiconductor material substantially fills said recesses and extends through at least a portion of said openings in said active semiconductor layer.

6. The transistor of claim 1, further comprising an air gap positioned in each of said recesses, wherein said air gap is positioned below at least a portion of said epi semiconductor material positioned in at least said recesses and above said bulk semiconductor layer of said SOI substrate.

7. The transistor of claim 1, wherein said epi semiconductor material positioned in at least said recesses comprises a doped epi semiconductor material that substantially fills said recesses and wherein said doped epi semiconductor material has an upper surface that is positioned at a level that is above a level of an upper surface of said active semiconductor layer.

8. The transistor of claim 3, wherein a portion of said second doped epi semiconductor material is positioned on and in contact with said upper surface of said active semiconductor layer.

9. The transistor of claim 1, wherein a portion of said epi semiconductor material positioned in at least said recesses in said buried insulation layer contacts and engages a lower surface of said active semiconductor layer.

10. A transistor formed above a semiconductor-on-insulator (SOI) substrate comprising a bulk semiconductor layer, a buried insulation layer positioned on said bulk semiconductor layer and an active semiconductor layer positioned on said buried insulation layer, said transistor comprising:

a gate structure, a sidewall spacer and source/drain regions;

openings extending through said active semiconductor layer of said SOI substrate in said source/drain regions adjacent said sidewall spacer;

recesses in said buried insulation layer of said SOI substrate in said source/drain regions of said transistor, wherein said recesses extend laterally under a portion of said active semiconductor layer;

a first substantially un-doped epi semiconductor material that is positioned at least partially within said recesses, wherein a portion of said buried insulation layer is positioned between said first substantially un-doped epi semiconductor material positioned in at least said recesses and said bulk semiconductor layer of said SOI substrate; and

a second doped epi semiconductor material that is positioned on said first substantially un-doped epi semiconductor material in said source/drain regions, wherein said second doped epi semiconductor material has an upper surface that is positioned at a level that is above a level of an upper surface of said active semiconductor layer.

11. The transistor of claim 10, wherein said first substantially un-doped epi semiconductor material and said second doped epi semiconductor material are comprised of different semiconductor materials.

12. The transistor of claim 10, wherein said first substantially un-doped epi semiconductor material substantially fills said recesses.

13. The transistor of claim 10, wherein a portion of said first substantially un-doped epi semiconductor material positioned in at least said recesses in said buried insulation layer contacts and engages a lower surface of said active semiconductor layer.

14. The transistor of claim 10, further comprising an air gap positioned in each of said recesses, wherein said air gap is positioned below at least a portion of said first substantially un-doped epi semiconductor material positioned in at least said recesses and above said bulk semiconductor layer of said SOI substrate.

15. The transistor of claim 10, wherein a portion of said second doped epi semiconductor material is positioned on and in contact with said upper surface of said active semiconductor layer.

16. A transistor formed above a semiconductor-on-insulator (SOI) substrate comprising a bulk semiconductor layer, a buried insulation layer positioned on said bulk semiconductor layer and an active semiconductor layer positioned on said buried insulation layer, said transistor comprising:

a gate structure, a sidewall spacer and source/drain regions;

openings extending through said active semiconductor layer of said SOI substrate in said source/drain regions adjacent said sidewall spacer;

recesses in said buried insulation layer of said SOI substrate in said source/drain regions of said transistor, wherein said recesses extend laterally under a portion of said active semiconductor layer; and

a doped epi semiconductor material that at least partially fills said recesses, substantially fills said openings in said active semiconductor layer, wherein said doped epi semiconductor material has an upper surface that is positioned at a level that is above a level of an upper surface of said active semiconductor layer, wherein a portion of said buried insulation layer is positioned between said doped epi semiconductor material positioned in at least said recesses and the bulk semiconductor layer of said SOI substrate.

17. The transistor of claim 16, wherein said doped epi semiconductor material substantially fills said recesses.

18. The transistor of claim 16, further comprising an air gap positioned in each of said recesses, wherein said air gap is positioned below at least a portion of said doped epi semiconductor material positioned in at least said recesses and above said bulk semiconductor layer of said SOI substrate.

19. The transistor of claim 16, wherein a first portion of said doped epi semiconductor material is positioned on and in contact with said upper surface of said active semiconductor layer and a second portion of said doped epi semiconductor material is positioned on and in contact with a lower surface of said active semiconductor layer.

20. The transistor of claim 16, wherein said gate structure has a vertical height above said upper surface of said active semiconductor layer and wherein said upper surface of said doped epi semiconductor material is positioned at a distance above said upper surface of said active semiconductor layer that is at least equal to one-half of said vertical height of said gate structure.