METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

• US 20200135897A1
• Filed: 02/11/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: DURIEZ, Blandine, VELLIANITIS, Georgios, DOORNBOS, Gerben, VAN DAL, Marcus Johannes Henricus, HOLLAND, Martin Christopher, VASEN, Timothy
• Granted Patent: US 11,004,958 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a dummy gate structure over a channel region of a semiconductor layer;

forming a source/drain epitaxial layer on opposing sides of the dummy gate structure;

performing a planarization operation on the source/drain epitaxial layer;

patterning the planarized source/drain epitaxial layer;

removing the dummy gate structure to form a gate space; and

forming a metal gate structure in the gate space.

2. The method of claim 1, further comprising forming first gate sidewall spacers on opposite side faces of the dummy gate structure before the source/drain epitaxial layer is formed.

3. The method of claim 2, further comprising, after the gate space is formed, forming second gate sidewall spacers on the first gate sidewall spacers in the gate space.

4. The method of claim 3, wherein the dummy gate structure includes a dummy gate electrode layer made of poly crystalline or amorphous SiGe or Ge.

5. The method of claim 1, wherein the source/drain epitaxial layer is formed such that a top of the source/drain epitaxial layer is located above the dummy gate structure.

6. The method of claim 5, wherein the source/drain epitaxial layer is formed such that the source/drain epitaxial layer fully covers the dummy gate structure.

7. The method of claim 1, wherein the source/drain epitaxial layer is formed at a temperature from 250°

C. to 450°

C.

8. The method of claim 1, further comprising:

forming a first interlayer dielectric (ILD) layer over the planarized source/drain epitaxial layer and the dummy gate structure; and

performing a planarization operation on the first ILD layer so that upper surfaces of the planarized source/drain epitaxial layer and the dummy gate structure are exposed.

9. The method of claim 8, further comprising:

forming a second ILD layer over the metal gate structure; and

forming a source/drain contact.

10. The method of claim 1, wherein:

the semiconductor device is formed over a silicon-on-insulator (SOI) substrate, and

the semiconductor layer is a silicon layer of the SOI substrate.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a semiconductor layer on a dielectric layer disposed over a substrate;

forming a dummy gate structure over a channel region of the semiconductor layer;

forming a source/drain epitaxial layer on opposing sides of the dummy gate structure;

performing a planarization operation on the source/drain epitaxial layer;

patterning the planarized source/drain epitaxial layer;

removing the dummy gate structure to form a gate space; and

forming a metal gate structure in the gate space.

12. The method of claim 11, further comprising forming first gate sidewall spacers on opposite side faces of the dummy gate structure before the source/drain epitaxial layer is formed.

13. The method of claim 12, further comprising forming second gate sidewall spacers on the first gate sidewall spacers in the gate space.

14. The method of claim 13, wherein the dummy gate structure includes a dummy gate electrode layer made of poly crystalline or amorphous SiGe or Ge.

15. The method of claim 11, wherein the source/drain epitaxial layer is formed such that a top of the source/drain epitaxial layer is located above the dummy gate structure.

16. The method of claim 15, wherein the source/drain epitaxial layer is formed such that the source/drain epitaxial layer fully covers the dummy gate structure.

17. The method of claim 11, wherein the source/drain epitaxial layer is formed at a temperature from 250°

C. to 450°

C.

18. The method of claim 11, further comprising:

forming a first interlayer dielectric (ILD) layer over the planarized source/drain epitaxial layer and the dummy gate structure; and

performing a planarization operation on the first ILD layer so that upper surfaces of the planarized source/drain epitaxial layer and the dummy gate structure are exposed.

19. The method of claim 18, comprising:

forming a field effect transistor (FET) over the substrate; and

forming the dielectric layer to cover the FET.

20. A semiconductor device comprising:

a channel formed as a part of a semiconductor layer disposed on a dielectric layer;

a gate dielectric layer disposed over the channel;

a gate electrode layer disposed over the gate dielectric layer;

gate sidewall spacers disposed on opposite side faces of the gate electrode layer; and

a source and a drain, each including an epitaxial layer,

wherein a height difference between an upper most portion of the epitaxial layer and an uppermost portion of the gate electrode layer is less than 5 nm.