SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20200135901A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHANG, Jung-Hao, LIN, Li-Te
• Granted Patent: US 11,107,907 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a dummy gate structure on a semiconductor fin;

forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;

removing the dummy gate structure from the semiconductor fin;

forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer;

performing a first plasma etching process by using a first reactant to etch back the gate structure; and

performing a second plasma etching process by using a second reactant on the gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.

2. The method of claim 1, wherein the second reactant is bromine-containing gases.

3. The method of claim 2, wherein the bromine-containing gases comprises hydrogen bromide.

4. The method of claim 1, wherein the first reactant comprises chlorine-containing gases.

5. The method of claim 1, wherein the first reactant is free from bromine-containing gases.

6. The method of claim 1, wherein the performing the second plasma etching process by using the second reactant is performed after the performing the first plasma etching process by using the first reactant.

7. The method of claim 1, further comprising:

after the performing the second plasma etching process, performing an ashing process on the gate structure.

8. The method of claim 1, wherein the gate dielectric layer comprises high-k dielectric materials.

9. A method for manufacturing a semiconductor device, comprising:

forming a dummy gate structure on a semiconductor substrate;

forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;

removing the dummy gate structure from the semiconductor substrate;

forming a gate structure on the semiconductor substrate and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer;

forming a protection layer over the work function metal of the gate structure while leaving the gate dielectric layer of the gate structure uncovered; and

performing a first etching back process on the gate dielectric layer of the gate structure.

10. The method of claim 9, wherein the first etching back process is performed simultaneously with the forming the protection layer.

11. The method of claim 9, wherein the protection layer comprises metal bromide.

12. The method of claim 9, wherein the performing the first etching back process on the gate dielectric layer of the structure comprises introducing a bromine-containing gas on the gate structure.

13. The method of claim 12, wherein the bromine-containing gas has a first removal rate of the protection layer and a second removal rate of the gate dielectric layer, and a first ratio of the first removal rate of the protection layer to the second removal rate of the gate dielectric layer is greater than about 5.

14. The method of claim 12, wherein the performing the first etching back process on the gate dielectric layer of the gate structure further comprises introducing a chlorine-containing gas on the etched-back gate structure.

15. The method of claim 14, wherein an amount of the bromine-containing gas is greater than an amount of the chorine-containing gas.

16. The method of claim 9, further comprising performing a second etching back process on the gate structure prior to the forming the protection layer over the work function metal.

17. The method of claim 16, wherein the second plasma etching process has a first removal rate of the work function metal and a second removal rate of the gate dielectric layer, and the first removal rate is greater than the second removal rate.

18. The method of claim 9, further comprising removing the protection layer from the work function metal.

19. A semiconductor device, comprising:

a substrate;

a semiconductor fin on the substrate;

a plurality of gate spacers over the semiconductor fin; and

a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises;

a gate dielectric layer; and

a work function metal over the gate dielectric layer, wherein a top surface of the work function metal is lower than a top surface of the gate dielectric layer, and a distance between the top surface of the work function metal and the top surface of the gate dielectric layer is less than about 1 nm.

20. The semiconductor device of claim 19, wherein a dielectric cap is atop the gate structure and between the gate spacers, wherein the dielectric cap and the a top surface of the gate dielectric layer have a first interface therebetween, the dielectric cap and the a top surface of the work function metal have a second interface therebetween, and a distance between the first and second interfaces is less than about 1 nm.