METHOD OF FORMING SHAPED SOURCE/DRAIN EPITAXIAL LAYERS OF A SEMICONDUCTOR DEVICE

• US 20200135903A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Yi-Jing, YU, Ming-Hua
• Granted Patent: US 11,056,578 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Claims

1. A semiconductor device, comprising:

a fin field-effect-transistor (Fin FET) device including;

a fin structure protruding from a substrate layer in a first direction and extending in a second direction perpendicular to the first direction;

a source/drain (SD) epitaxial structure disposed on the fin structure;

a gate stack including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure and extending in the second direction; and

a dielectric layer over sidewalls of the fin structure in a region of the SD epitaxial structure not covered by the gate stack, wherein the dielectric layer extends an entire length of the region of the SD epitaxial structure in the second direction, and wherein the SD epitaxial structure has a diamond shape top with limited lateral growth in the second direction and including flat side surfaces parallel to the first direction, and wherein an extent of the SD epitaxial structure in the second direction is limited to about outer sidewalls of the dielectric layer in the region of the SD epitaxial structure, the outer sidewalls of the dielectric layer are further away from the SD epitaxial structure.

2. The semiconductor device of claim 1, further comprising:

an isolation insulating layer disposed over the substrate layer, wherein a first portion of the fin structure protrudes outward from the isolation insulating layer and is exposed from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer.

3. The semiconductor device of claim 2, wherein the isolation insulating layer comprises a shallow trench isolation (STI) material.

4. The semiconductor device of claim 2, wherein the dielectric layer covers the sidewalls of the first portion of the fin structure in the region of the SD epitaxial structure.

5. The semiconductor device of claim 4, wherein the dielectric layer that covers the sidewalls of the first portion of the fin structure in the region of the SD epitaxial structure is asymmetric.

6. The semiconductor device of claim 4, wherein the SD epitaxial structure formed over the asymmetric sidewalls is asymmetric.

7. The semiconductor device of claim 1, wherein a top surface of the fin structure under the SD epitaxial structure has a preferred crystallographic facet.

8. The semiconductor device of claim 7, wherein the preferred crystallographic facet comprise a (100) facet.

9. The semiconductor device of claim 1, wherein the semiconductor device comprises a PMOS device.

10. A semiconductor device, comprising:

a fin structure disposed on a substrate, the fin structure protruding from the substrate in a first direction and extending in a second direction perpendicular to the first direction;

an isolation insulating layer disposed over the fin structure, wherein a first portion of the fin structure is exposed from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer;

a gate structure disposed over a part of the first portion of the fin structure;

a source/drain (SD) epitaxial structure disposed on opposite sides of the gate structure in an S/D region; and

a dielectric layer disposed over sidewalls of the first portion of the fin structure in the S/D region not covered by the gate structure, wherein the dielectric layer extends an entire length of the S/D region in the second direction, and wherein an extent of the SD epitaxial structure in the second direction is limited to about outer sidewalls of the dielectric layer in a region of the SD epitaxial structure, the outer sidewalls of the dielectric layer are further away from the SD epitaxial structure.

11. The semiconductor device of claim 10, wherein the semiconductor device comprises a NMOS device.

12. The semiconductor device of claim 10, wherein the dielectric layer comprises silicon nitride (Si₃N₄), silicon oxide (SiO₂), or silicon oxynitride (SiO_xN_y).

13. The semiconductor device of claim 10, wherein side surfaces of the SD epitaxial structure in the second direction are flat.

14. The semiconductor device of claim 13, wherein the side surfaces of the SD epitaxial structure in the second direction are above the outer sidewalls of the dielectric layer.

15. The semiconductor device of claim 10, wherein the SD epitaxial structure has a diamond shape top.

16. The semiconductor device of claim 10, wherein a ratio of a height of the SD epitaxial structure over a height of the dielectric layer in the S/D region is between 5.6 to 6.2.

17. A semiconductor device, comprising:

a first structure including a fin made of a first material disposed on a substrate, the first structure extends in a first direction, the first structure comprises a first portion exposed and a second portion embedded;

a gate structure disposed over a part of the first portion of the fin;

a dielectric layer disposed over sidewalls of the first portion of the fin in a source/drain region not covered by the gate structure, wherein the dielectric layer extends an entire length of the source/drain region in the first direction; and

a source/drain (SD) epitaxial structure disposed in the source/drain region, an extent of a top part of the SD epitaxial structure in a second direction perpendicular to the first direction is limited to outer sidewalls of the dielectric layer in the source/drain region, wherein the outer sidewalls of the dielectric layer are further away from the SD epitaxial structure, and wherein the top part of the SD epitaxial structure includes flat side surfaces perpendicular to the first direction.

18. The semiconductor device of claim 17, wherein the dielectric layer that covers the sidewalls of the first portion of the fin structure in the source/drain region is asymmetric.

19. The semiconductor device of claim 17, wherein the SD epitaxial structure formed over the asymmetric sidewalls is asymmetric.

20. The semiconductor device of claim 19, wherein the flat side surfaces of the SD epitaxial structure in the second direction are above the outer sidewalls of the dielectric layer.