ONE-TRANSISTOR DRAM CELL DEVICE HAVING QUANTUM WELL STRUCTURE

• US 20200135905A1
• Filed: 10/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Gachon University of Industry-Academic Cooperation Foundation
• Original Assignee: Gachon University of Industry-Academic Cooperation Foundation
• Inventors: Cho, Seongjae, Yu, EunSeon, Lee, Jae Yoon
• Granted Patent: US 11,158,732 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.

Claims

1. A 1T DRAM cell device comprising:

a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,

wherein the body region has a first semiconductor layer and a second semiconductor layer formed in a channel length direction with a first heterojunction surface, the first heterojunction surface being perpendicular to the channel length direction,

wherein the first semiconductor layer is formed of the same semiconductor material as that of the source region and has a homojunction with the source region,

wherein the second semiconductor layer is formed of a semiconductor material different from the drain region to be in contact with a second heterojunction surface perpendicular to the channel length direction, and

wherein the charge is stored in a quantum well formed by the first heterojunction surface and the second heterojunction surface in the second semiconductor layer.

2. The 1T DRAM cell device of claim 1, wherein the second semiconductor layer has an energy band gap smaller than those of the first semiconductor layer and the drain region.

3. The 1T DRAM cell device of claim 2, wherein the first semiconductor layer is formed to protrude vertically on the source region, and the second semiconductor layer and the drain region are sequentially stacked on the first semiconductor layer.

4. The 1T DRAM cell device of claim 2, wherein the body region has a polygonal pillar vertically stacked with the first semiconductor layer and the second semiconductor layer on the source region, and the gate is two or more gates circumferentially spaced on the polygonal pillar.

5. The 1T DRAM cell device of claim 2, wherein the source region and the drain region are horizontally spaced apart on the semiconductor substrate, and the first semiconductor layer and the second semiconductor layer are horizontally formed between the source region and the drain region.

6. The 1T DRAM cell device of claim 2, wherein the source region and the drain region are horizontally spaced apart on the semiconductor substrate, the body region is a polygonal horizontal bar formed with the first semiconductor layer and the second semiconductor layer between the source region and the drain region, and the gate is two or more gates circumferentially spaced on the polygonal horizontal bar.

7. The 1T DRAM cell device of claim 1, wherein the gate is two or more gates covering the first heterojunction surface and the second heterojunction surface and spaced apart from the source region by a predetermined distance.

8. The 1T DRAM cell device of claim 7, wherein the first semiconductor layer is a silicon layer having a conductivity type opposite to that of the source region, and the second semiconductor layer is a silicon germanium layer doped with a higher concentration than the first semiconductor layer in the same conductivity type as the first semiconductor layer.

9. The 1T DRAM cell device of claim 8, wherein the silicon layer is formed of a bulk silicon substrate together with the source region.

10. A 1T DRAM cell device comprising:

a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,

wherein the body region has a first semiconductor layer and a second semiconductor layer formed in a channel length direction with a first heterojunction surface, the first heterojunction surface being perpendicular to the channel length direction,

wherein the first semiconductor layer is formed of the same semiconductor material as that of the source region and has a homojunction with the source region,

wherein the second semiconductor layer is formed of a semiconductor material different from the drain region to be in contact with a second heterojunction surface perpendicular to the channel length direction,

wherein the charge is stored in a quantum well formed by the first heterojunction surface and the second heterojunction surface in the second semiconductor layer, and

wherein the gate is two or more gates formed on the second semiconductor layer separated from the source region by the first semiconductor layer.

11. A 1T DRAM cell device comprising:

a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,

wherein the body region has a first semiconductor layer and a second semiconductor layer formed in a channel length direction, the second semiconductor layer being inserted in the first semiconductor layer with a predetermined length from one side of the drain in the channel length direction and having a first heterojunction surface perpendicular to the channel length direction and one or more third heterojunction surfaces parallel to the channel length direction,

wherein the first semiconductor layer is formed of the same semiconductor material as that of the source region and has a homojunction with the source region,

wherein the second semiconductor layer is formed of a semiconductor material different from the drain region to be in contact with a second heterojunction surface perpendicular to the channel length direction, and

wherein the charge is stored in a quantum well formed by the first heterojunction surface, the second heterojunction surface and the third heterojunction surfaces in the second semiconductor layer.

12. A 1T DRAM cell device comprising:

a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,

wherein the body region has two or more heterojunction surfaces perpendicular to a channel length direction by repeatedly forming a first semiconductor layer and a second semiconductor layer alternately in heterojunction in the channel length direction, and

wherein the source region and the drain region are formed of the same semiconductor material as the semiconductor layer in contact with one of the first semiconductor layer and the second semiconductor layer, respectively.

13. The 1T DRAM cell device of claim 12, wherein the semiconductor layer in contact with the drain region is formed to have a thickness equal to or smaller than that of the gate insulating layer.

14. A 1T DRAM cell device comprising:

a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,

wherein the body region has a first semiconductor layer and a second semiconductor layer formed in a channel length direction with a first heterojunction surface, the first heterojunction surface being perpendicular to the channel length direction,

wherein the second semiconductor layer is formed of a semiconductor material different from the drain region to be in contact with a second heterojunction surface perpendicular to the channel length direction,

wherein the first semiconductor layer is formed of a semiconductor material different from the source region to be in contact with a third heterojunction surface perpendicular to the channel length direction,

wherein the charge is stored in the quantum well formed by the first heterojunction surface and the second heterojunction surface in the second semiconductor layer, and

wherein the gate is two or more gates formed on the second semiconductor layer separated from the source region by the first semiconductor layer.

15. The 1T DRAM cell device of claim 14, wherein the drain region is formed of the same semiconductor material as that of the first semiconductor layer, and the second semiconductor layer has an energy band gap smaller than those of the first semiconductor layer and the drain region.

16. The IT DRAM cell device of claim 15, wherein the first semiconductor layer has the same conductivity type as the source region.

17. The 1T DRAM cell device of claim 14, wherein the body region has a square pillar vertically stacked with the first semiconductor layer and the second semiconductor layer on the source region, the gate is four gates circumferentially spaced on the square pillar, and at least one of the four gates is a hold gate to apply a hold voltage for maintaining the charge in the quantum well.

18. The 1T DRAM cell device of claim 17, wherein the first semiconductor layer is a silicon carbon layer, and the second semiconductor layer is a silicon layer having a conductivity type opposite to that of the first semiconductor layer.