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ONE-TRANSISTOR DRAM CELL DEVICE HAVING QUANTUM WELL STRUCTURE

  • US 20200135905A1
  • Filed: 10/22/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/24/2018
  • Status: Active Grant
First Claim
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1. A 1T DRAM cell device comprising:

  • a body region connecting a source region and a drain region and storing charge, and at least one gate formed on the body region with a gate insulating layer interposed therebetween,wherein the body region has a first semiconductor layer and a second semiconductor layer formed in a channel length direction with a first heterojunction surface, the first heterojunction surface being perpendicular to the channel length direction,wherein the first semiconductor layer is formed of the same semiconductor material as that of the source region and has a homojunction with the source region,wherein the second semiconductor layer is formed of a semiconductor material different from the drain region to be in contact with a second heterojunction surface perpendicular to the channel length direction, andwherein the charge is stored in a quantum well formed by the first heterojunction surface and the second heterojunction surface in the second semiconductor layer.

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