METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20200135908A1
• Filed: 05/31/2017
• Published: 04/30/2020
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: NANJO, Takuma, HAYASHIDA, Tetsuro, YOSHITSUGU, Koji, FURUKAWA, Akihiko
• Granted Patent: US 11,282,950 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Al_x1In_y1Ga_1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Al_x2In_y2Ga_1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.

Claims

1. A method for manufacturing semiconductor device comprising:

forming a channel layer that is Al_x1In_y1Ga_1-x1-y1N (where 0≤

x1≤

1, 0≤

y1≤

1) on an upper surface of a semiconductor substrate;

forming a barrier layer that is Al_x2In_y2Ga_1-x2-y2N (where 0≤

x2≤

1, 0≤

y2≤

1) having a band gap larger than a band gap of the channel layer on an upper surface of the channel layer;

at least partially forming a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer, on an upper surface of the barrier layer;

forming a gate electrode on an upper surface of the gate insulating film; and

performing heat treatment while applying a positive voltage to the gate electrode.

2. The method for manufacturing semiconductor device according to claim 1, further comprising

forming a plurality of first impurity regions reaching the channel layer from the upper surface of the barrier layer, wherein

the forming the gate insulating film is forming the gate insulating film at least on the upper surface of the barrier layer between the first impurity regions in plan view.

3. The method for manufacturing semiconductor device according to claim 2, wherein

the forming the gate electrode is forming the gate electrode on the upper surface of the gate insulating film, in a range not overlapping with the first impurity region in plan view.

4. The method for manufacturing semiconductor device according to claim 2, wherein

the forming the gate electrode is forming the gate electrode on the upper surface of the gate insulating film, in a range where an end portion of the gate electrode coincides with the first impurity region in plan view.

5. The method for manufacturing semiconductor device according to claim 2, further comprising

forming a second impurity region reaching the channel layer from the upper surface of the barrier layer and being sandwiched between the first impurity regions in plan view, wherein

an impurity concentration of the second impurity region is lower than an impurity concentration of the first impurity region.

6. The method for manufacturing semiconductor device according to claim 5, wherein

the forming the second impurity region is forming the second impurity region at a position adjacent to the first impurity region.

7. The method for manufacturing semiconductor device according to claim 1, wherein

the performing the heat treatment is performing the heat treatment at a temperature of 250°

C. or more for 60 seconds or more while applying +5 V as a positive voltage to the gate electrode.

8. The method for manufacturing semiconductor device according to claim 1, wherein

the performing the heat treatment is performing the heat treatment in an atmosphere having an oxygen concentration of 20% or more while applying a positive voltage to the gate electrode.

9. The method for manufacturing semiconductor device according to claim 1, wherein

in a state where no voltage is applied to the gate electrode, energy at a lower end of a conduction band at a heterointerface between the channel layer and the barrier layer located below the gate electrode is higher than Fermi energy.

10. The method for manufacturing semiconductor device according to claim 1, wherein

the forming the channel layer is forming the channel layer that is GaN on the upper surface of the semiconductor substrate.

11. The method for manufacturing semiconductor device according to claim 1, wherein

the forming the barrier layer is forming the barrier layer that is AlGaN on the upper surface of the channel layer.

12. The method for manufacturing semiconductor device according to claim 1, wherein

the forming the barrier layer is forming the barrier layer that is InAlN on the upper surface of the channel layer.

13. The method for manufacturing semiconductor device according to claim 1, wherein

the forming the barrier layer is forming the barrier layer that is AlN on the upper surface of the channel layer.

14. The method for manufacturing semiconductor device according to claim 1, wherein

the forming the gate insulating film is at least partially forming the gate insulating film that is AlO on the upper surface of the barrier layer.

15. A method for manufacturing semiconductor device comprising:

forming a channel layer that is Al_x1In_y1Ga_1-x1-y1N (where 0≤

x1≤

1, 0≤

y1≤

1) on an upper surface of a semiconductor substrate;

at least partially forming a gate insulating film that is an insulator or a semiconductor and has a band gap larger than a band gap of the channel layer on an upper surface of the channel layer;

forming a gate electrode on an upper surface of the gate insulating film; and

performing heat treatment while applying a positive voltage to the gate electrode.