SEMICONDUCTOR DEVICE

• US 20200135909A1
• Filed: 10/28/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Application

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: TANAKA, Taketoshi
• Application Number:
  US16/665,501
• Publication Number:
  US 20200135909A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A semiconductor devices includes: a conductive substrate; an electron transit layer arranged on the conductive substrate; an electron supply layer arranged on the electron transit layer; and a source electrode, a drain electrode, and a gate electrode arranged on the electron supply layer, wherein the electron transit layer includes a nitride semiconductor layer including an acceptor type impurity, and wherein the semiconductor device has a characteristic that when a negative bias is applied to the conductive substrate, a source-drain resistance decreases over time.

Claims

1. A semiconductor device, comprising:

a conductive substrate;

an electron transit layer arranged on the conductive substrate;

an electron supply layer arranged on the electron transit layer; and

a source electrode, a drain electrode, and a gate electrode arranged on the electron supply layer,

wherein the electron transit layer includes a nitride semiconductor layer including an acceptor type impurity, and

wherein the semiconductor device has a characteristic that when a negative bias is applied to the conductive substrate, a source-drain resistance decreases over time.

3. The device of claim 1, wherein the electron transit layer includes the nitride semiconductor layer, and a conduction path forming layer which is formed between the nitride semiconductor layer and the electron supply layer and whose surface is in contact with the electron supply layer.

4. The device of claim 1, wherein an activation energy of a temperature characteristic of a source-drain resistance change rate is 0.5 eV or more and 0.7 eV or less.

5. The device of claim 1, wherein a deep donor level of the nitride semiconductor layer is within a range of 0.5 eV or more and 0.7 eV or less from a conduction band.

6. The device of claim 1, wherein the acceptor type impurity is carbon, and a carbon density of the nitride semiconductor layer is 1×

10¹⁹ cm<sup>−

3</sup> or more and 8×

10¹⁹ cm<sup>−

3</sup> or less.

7. The device of claim 1, wherein the nitride semiconductor layer includes a vacancy defect VGa(VN)n including one gallium vacancy and two nitrogen vacancies.

2. A semiconductor device, comprising:

a substrate;

an electron transit layer arranged on the substrate;

an electron supply layer arranged on the electron transit layer; and

a source electrode, a drain electrode, and a gate electrode arranged on the electron supply layer,

wherein the electron transit layer includes a nitride semiconductor layer including an acceptor type impurity, and

wherein a deep donor density of the nitride semiconductor layer is larger than a deep acceptor density of the nitride semiconductor layer.

8. A semiconductor device, comprising:

a substrate;

an electron transit layer arranged on the substrate;

an electron supply layer arranged on the electron transit layer; and

a source electrode, a drain electrode, and a gate electrode arranged on the electron supply layer,

wherein the electron transit layer includes a nitride semiconductor layer including an acceptor type impurity, and

wherein the acceptor type impurity is carbon, and a carbon density of the nitride semiconductor layer is 1×

10¹⁹ cm<sup>−

3</sup> or more and 8×

10¹⁹ cm<sup>−

3</sup> or less.