APPARATUS AND CIRCUITS WITH DUAL THRESHOLD VOLTAGE TRANSISTORS AND METHODS OF FABRICATING THE SAME

• US 20200135911A1
• Filed: 09/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHERN, Chan-Hong
• Granted Patent: US 10,971,616 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

Claims

1. A semiconductor structure, comprising:

a substrate;

an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness;

a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and

a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

2. The semiconductor structure of claim 1, wherein:

the first transistor and the second transistor are high electron mobility transistors to be used in a same multi-stage driver circuit.

3. The semiconductor structure of claim 1, wherein:

the first transistor has a first threshold voltage; and

the second transistor has a second threshold voltage that is lower than the first threshold voltage.

4. The semiconductor structure of claim 3, wherein:

the first active portion is thinner than the second active portion.

5. The semiconductor structure of claim 4, wherein:

the first thickness is smaller than 80% of the second thickness.

6. The semiconductor structure of claim 1, further comprising a channel layer formed over the substrate and below the active layer, wherein:

the channel layer comprises a first III-V semiconductor material; and

the active layer comprises a second III-V semiconductor material that is different from the first III-V semiconductor material.

7. The semiconductor structure of claim 6, wherein:

the first III-V semiconductor material comprises gallium nitride (GaN); and

the second III-V semiconductor material comprises aluminum gallium nitride (AlGaN).

8. The semiconductor structure of claim 1, further comprising a polarization modulation layer that comprises a first polarization modulation portion disposed on the first active portion and a second polarization modulation portion disposed on the second active portion, wherein:

the polarization modulation layer comprises p-type doped GaN;

the first gate structure is disposed on the first polarization modulation portion;

the second gate structure is disposed on the second polarization modulation portion; and

the first polarization modulation portion has a thickness different from that of the second polarization modulation portion.

9. A circuit, comprising:

a first transistor including a first gate, a first source and a first drain; and

a second transistor including a second gate, a second source and a second drain, wherein;

the first transistor and the second transistor are formed on a same semiconductor wafer including an active layer that comprises a first active portion under the first gate and a second active portion under the second gate,

the first active portion has a first thickness, and

the second active portion has a second thickness different from the first thickness.

10. The circuit of claim 9, wherein:

the first transistor has a first threshold voltage; and

the second transistor has a second threshold voltage that is different from the first threshold voltage.

11. The circuit of claim 9, wherein:

at least one of the first source and the first drain is electrically connected to a ground voltage; and

at least one of the second source and the second drain is electrically connected to a positive supply voltage.

12. The circuit of claim 11, wherein:

the first threshold voltage is higher than the second threshold voltage.

13. The circuit of claim 12, wherein:

the first active portion is thinner than the second active portion.

14. The circuit of claim 12, wherein:

at least one of the first source and the first drain is electrically connected to an output pin of the circuit.

15. The circuit of claim 12, wherein the first transistor is at least one of:

a high voltage enhancement-mode high electron mobility transistor (HV E-HEMT);

a low voltage enhancement-mode high electron mobility transistor (LV E-HEMT); and

a low voltage depletion-mode high electron mobility transistor (LV D-HEMT).

16. The circuit of claim 12, wherein the second transistor is a low voltage enhancement-mode high electron mobility transistor (LV E-HEMT).

17. The circuit of claim 9, wherein the first gate is physically coupled to the second source.

18. A method for forming a semiconductor structure, comprising:

forming an active layer over a substrate, wherein the active layer comprises a first active portion having a first thickness and a second active portion having a second thickness;

forming a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and

forming a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

19. The method of claim 18, wherein:

the first transistor and the second transistor are high electron mobility transistors to be used in a same multi-stage driver circuit;

the first transistor has a first threshold voltage;

the second transistor has a second threshold voltage that is lower than the first threshold voltage; and

the first active portion is thinner than the second active portion.

20. The method of claim 18, wherein forming the active layer comprises:

forming a first sub-layer over the substrate;

forming a second sub-layer on the first sub-layer with a mask covering part of the first sub-layer, wherein each of the first sub-layer and the second sub-layer comprises aluminum gallium nitride (AlGaN); and

removing the mask to form the first active portion and the second active portion that have different thicknesses.