FINFET DEVICE AND METHODS OF FORMING THE SAME

• US 20200135913A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: More, Shahaji B., Chang, Shih-Chieh, Lee, Cheng-Han
• Granted Patent: US 10,868,183 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

Claims

1. A semiconductor device comprising:

a substrate;

a fin protruding above the substrate, the fin comprising a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, wherein a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate;

a gate structure over the fin;

a channel region in the fin and directly under the gate structure; and

source/drain regions on opposing sides of the gate structure, the source/drain regions comprising a second dopant, wherein a concentration of the second dopant in the channel region changes along the first direction, wherein the concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, wherein the concentration of the first dopant at the first location is lower than that at the second location.

2. The semiconductor device of claim 1, wherein the compound semiconductor material is silicon germanium, the semiconductor material is silicon, and the first dopant is germanium.

3. The semiconductor device of claim 1, wherein the channel region comprises a first segment, the concentration of the first dopant in the first segment increases along the first direction, and the concentration of the second dopant in the first segment decreases continuously along the first direction.

4. The semiconductor device of claim 1, further comprising a capping layer over the channel region of the fin, wherein the capping layer is substantially free of the first dopant.

5. The semiconductor device of claim 1, wherein the fin comprises a first segment, the concentration of the first dopant in the first segment increases continuously along the first direction.

6. The semiconductor device of claim 5, wherein the fin further comprises a second segment between the first segment and the substrate, the concentration of the first dopant in the second segment is lower than a lowest concentration of the first dopant in the first segment.

7. The semiconductor device of claim 6, wherein the fin further comprises a third segment between the first segment and the second segment, and the concentration of the first dopant in the third segment is uniform.

8. The semiconductor device of claim 7, wherein the concentration of the first dopant in the third segment is substantially equal to a highest concentration of the first dopant in the first segment.

9. The semiconductor device of claim 7, wherein the fin further comprises a fourth segment over the first segment, with the first segment between the fourth segment and the third segment, wherein the concentration of the first dopant in the fourth segment is uniform.

10. The semiconductor device of claim 9, wherein the concentration of the first dopant in the fourth segment is lower than the concentration of the first dopant in the third segment.

11. The semiconductor device of claim 1, wherein the fin comprises a buffer layer, a first sublayer over the buffer layer, and a second sublayer over the first sublayer, wherein the concentration of the first dopant in the first sublayer has a first value, the concentration of the first dopant in the second sublayer has a second value smaller than the first value, wherein the concentration of the first dopant in the buffer layer has a third value smaller than the second value.

12. A semiconductor device comprising:

a fin over a substrate, the fin comprising silicon germanium;

a gate structure over the fin;

a channel region in the fin, the gate structure being disposed over the channel region, a concentration of germanium in the channel region changing along a first direction from an upper surface of the fin distal from the substrate to the substrate, wherein a concentration of germanium increases from a first location of the channel region to a second location of the channel region, wherein the first location and the second location are aligned along the first direction; and

a source/drain region in the fin and adjacent to the gate structure, the source/drain region comprising a dopant, a concentration of the dopant in the channel region changing along the first direction, wherein a concentration of the dopant decreases from the first location of the channel region to the second location of the channel region.

13. The semiconductor device of claim 12, wherein the dopant is boron or antimony.

14. The semiconductor device of claim 12, wherein the source/drain region comprises a first sublayer, a second sublayer over the first sublayer, and a third sublayer over the second sublayer, wherein the first sublayer has a first concentration of the dopant, the second sublayer has a second concentration of the dopant, and the third sublayer has a third concentration of the dopant, wherein the third concentration is higher than the second concentration, and the second concentration is higher than the first concentration.

15. The semiconductor device of claim 12, wherein the fin comprises a gradient layer, wherein the concentration of germanium in the gradient layer increases along the first direction.

16. The semiconductor device of claim 15, wherein the fin further comprises a buffer layer between the gradient layer and the substrate, wherein the concentration of germanium in the buffer layer is lower than the concentration of germanium in the gradient layer.

17-20. -20. (canceled)

21. A semiconductor device comprising:

a fin protruding from a substrate, the fin comprising silicon germanium, wherein a concentration of germanium in the fin varies along a first direction from an upper surface of the fin toward the substrate;

a gate over a channel region of the fin, wherein a concentration of germanium in the channel region increases from a first location of the channel region to a second location of the channel region, wherein the first location and the second location are aligned along the first direction; and

a doped source/drain region in the fin and adjacent to the gate, wherein a dopant of the doped source/drain region diffuses into the channel region of the fin, wherein a concentration of the dopant in the channel region varies along the first direction, wherein the concentration of the dopant decreases from the first location of the channel region to the second location of the channel region.

22. The semiconductor device of claim 21, wherein the channel region of the fin between the first location and the second location form a gradient segment of the channel region, wherein the channel region of the fin further comprises a first segment between the gradient segment and the substrate, wherein a first concentration of germanium in the first segment is uniform.

23. The semiconductor device of claim 22, wherein the channel region of the fin further comprises a second segment over the gradient segment such that the gradient segment is between the second segment and the first segment, wherein a second concentration of germanium in the second segment is uniform.

24. The semiconductor device of claim 23, wherein the first concentration is higher than the second concentration.