VERTICAL TRANSISTOR WITH EXTENDED DRAIN REGION

• US 20200135916A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: MEHROTRA, Saumitra Raj, GROTE, Bernhard, RADIC, Ljubo
• Granted Patent: US 10,749,023 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Claims

1. A method for forming a transistor device comprising:

forming a vertical component sidewall in a semiconductor material, the vertical component sidewall separating an upper surface level and a lower surface level of the semiconductor material;

forming a first conductive sidewall spacer structure laterally adjacent to the vertical component sidewall, the first conductive sidewall spacer structure is utilized as a control terminal for a transistor;

forming a dielectric layer directly over the lower surface level, the dielectric layer including a portion adjacent to the first conductive sidewall spacer structure;

forming a second conductive sidewall spacer structure laterally adjacent to the first conductive sidewall spacer structure and directly over the portion of the dielectric layer and directly over the lower surface level, wherein the second conductive sidewall spacer structure is utilized as a field plate for the transistor;

forming a channel region for the transistor including a portion located in the vertical component sidewall;

forming a source region for the transistor in the semiconductor material directly under the upper surface level, the source region including a portion located above the channel region;

wherein the transistor includes an extended drain region in the semiconductor material including at least a portion located directly below the second conductive sidewall spacer structure.

2. The method of claim 1 wherein the forming the dielectric layer over the lower surface level includes utilizing a LOCOS process to form an oxide material.

3. The method of claim 2 wherein the oxide material formed by the LOCOS process include dielectric material formed directly under the previously formed first conductive sidewall spacer structure.

4. The method of claim 1 wherein the semiconductor material is part of a wafer, wherein the forming the first conductive sidewall spacer structure and the second conductive sidewall spacer structure includes planarizing the wafer to remove a top portion of the first conductive sidewall spacer structure and the second conductive sidewall spacer structure.

5. The method of claim 4 wherein after the planarizing, forming a field plate structure for the transistor, the field plate structure is located in an area of the wafer that is laterally between an area of the second conductive sidewall spacer structure and an area of a drain region for the transistor, wherein the area of the second conductive sidewall spacer structure is located laterally between an area of the first conductive sidewall spacer structure and the area of the field plate structure.

6. The method of claim 5 wherein the forming the field plate structure includes forming a layer of conductive material over the wafer and then patterning the layer of conductive material.

7. The method of claim 1 further comprising forming a field plate structure for the transistor, the field plate structure located in an area of a wafer that is laterally between an area of the second conductive sidewall spacer structure and an area of a drain region of the transistor, wherein the area of the second conductive sidewall spacer structure is located laterally between an area of the first conductive sidewall spacer structure and the area of the field plate structure.

8. The method of claim 7 wherein the field plate structure is characterized as a sidewall spacer structure laterally adjacent to the second conductive sidewall spacer structure, wherein the semiconductor material is located in a wafer, wherein the forming the first conductive sidewall spacer structure, the second conductive sidewall spacer structure, and the field plate structure includes planarizing the wafer to remove a top portion of the first conductive sidewall spacer structure, the second conductive sidewall spacer structure, and the field plate structure.

9. The method of claim 1 further comprising:

forming a second vertical component sidewall in a semiconductor material, the second vertical component sidewall separating a second upper surface level and the lower surface level of the semiconductor material, the second vertical component sidewall facing the vertical component sidewall;

forming a third conductive sidewall spacer structure laterally adjacent to the second vertical component sidewall, the third conductive sidewall spacer structure is utilized as a control terminal for a second transistor, wherein the dielectric layer includes a second portion laterally adjacent to the third conductive sidewall spacer structure;

forming a fourth conductive sidewall spacer structure laterally adjacent to the third conductive sidewall spacer structure and directly over the dielectric layer and directly over the lower surface level, wherein the fourth conductive sidewall spacer structure is utilized a field plate for the second transistor;

forming a second channel region for the second transistor including a portion located in the second vertical component sidewall;

forming a second source region for the second transistor in the semiconductor material directly under the second upper surface level, the second source region including in a portion located above the second channel region;

wherein the second transistor includes a second extended drain region including at least a portion located directly below the fourth conductive sidewall spacer structure.

10. The method of claim 9 further comprising:

forming a shared drain region for the transistor and the second transistor in the semiconductor material directly below the lower surface level.

11. The method of claim 9 wherein the extended drain region and the second extended drain region are characterized as virtual extended drain regions, wherein the transistor and the second transistor are coupled in a back-to-back configuration.

12. The method of claim 1 further comprising:

forming a drain region for the transistor device in the semiconductor material directly below the lower surface level.

13. The method of claim 1, further comprising:

forming a second vertical component sidewall in the semiconductor material, the second vertical component sidewall separating a second upper surface level and the lower surface level of the semiconductor material, the second vertical component sidewall facing the vertical component sidewall;

forming a drain region for the transistor in the semiconductor material directly below the second upper surface level.

14. A transistor device comprising:

a source region for a transistor located in a first portion of a semiconductor material, the first portion having an upper surface at a first level, a second portion of a semiconductor material has an upper surface at a second level that is lower than the first level, a sidewall of the semiconductor material separating the first portion from the second portion;

a control terminal sidewall spacer structure for the transistor laterally adjacent to the sidewall and located directly over the second portion, the control terminal sidewall spacer structure is vertically separated from the second portion by dielectric by a first vertical distance;

a field plate sidewall spacer structure for the transistor laterally adjacent to the sidewall and to the control terminal sidewall spacer structure, the field plate sidewall spacer structure located directly over the second portion, the field plate sidewall spacer structure vertically separated from the second portion by dielectric by a second vertical distance, the second vertical distance is greater than the first vertical distance;

a channel region for the transistor including a portion located in the sidewall laterally adjacent to the control terminal sidewall spacer structure and below the source region;

an extended drain region for the transistor, the extended drain region includes a portion located directly below the field plate sidewall spacer structure in the second portion.

15. The transistor device of claim 14 further comprising a drain region for the transistor located in the second portion of a semiconductor material.

16. The transistor device of claim 14 further comprising:

a field plate structure for the transistor located in an area laterally adjacent to an area of the field plate sidewall spacer structure and located directly over the extended drain region, the field plate structure vertically separated from the second portion by dielectric by a third vertical distance, the third vertical distance is greater than the second vertical distance.

17. The transistor device of claim 16 wherein the field plate structure is characterized as a photo-lithographically patterned structure.

18. The transistor device of claim 16 wherein the field plate structure is characterized as a sidewall spacer structure.

19. The transistor device of claim 16 wherein the field plate structure includes a top surface that is located above a top surface of the field plate sidewall spacer structure and a top surface of the control terminal sidewall spacer structure.

20. The transistor device of claim 16 wherein the control terminal sidewall spacer structure, the field plate sidewall spacer structure, and the field plate structure each have a top surface that is co-planar with each other.

21. The transistor device of claim 14 wherein the control terminal sidewall spacer structure and the field plate sidewall spacer structure each have a top surface that is co-planar with each other.

22. The transistor device of claim 14 wherein the control terminal sidewall spacer structure and the field plate sidewall spacer structure are electrically coupled together to be biased at a same potential.

23. The transistor device of claim 14 further comprising:

a second source region located in a third portion of a semiconductor material, the third portion having an upper surface at the first level;

a second sidewall of the semiconductor material separating the third portion from the second portion, the second sidewall facing the sidewall;

a second control terminal sidewall spacer structure laterally adjacent to the second sidewall and located directly over the second portion, the second control terminal sidewall spacer structure vertically separated from the second portion by dielectric by the first vertical distance;

a second field plate sidewall spacer structure laterally adjacent to the second sidewall and to the second control terminal sidewall spacer structure, the second field plate sidewall spacer structure located directly over the second portion, the second field plate sidewall spacer structure vertically separated from the second portion by dielectric by the second vertical distance;

a second channel region including a portion located in the second sidewall laterally adjacent to the second control terminal sidewall spacer structure and below the second source region;

a second extended drain region including a portion located directly below the second field plate sidewall spacer structure in the second portion.

24. The transistor device of claim 23 wherein the second control terminal sidewall spacer structure, the second source region, the second channel region, the second field plate sidewall spacer structure, and the second extended drain region are for a second transistor, wherein the transistor device includes a shared drain region in the second portion for the transistor and the second transistor.

25. The transistor device of claim 23 wherein the second control terminal sidewall spacer structure, the second source region, the second channel region, the second field plate sidewall spacer structure, and the second extended drain region are for a second transistor, the second transistor is in a back to back configuration with the transistor, wherein the extended drain region and the second extended drain region are characterized as virtual extended drain regions.

26. The transistor device of claim 14 wherein the control terminal sidewall spacer structure includes a first side and a second side, the first side is laterally closer to the sidewall than the second side, wherein the first side is vertically separated from the second portion by the first vertical distance and the second side is vertically separated from the second portion by a third vertical distance, where in the third vertical distance is greater than the first vertical distance.