LDMOS FIN-TYPE FIELD-EFFECT TRANSISTORS INCLUDING A DUMMY GATE

• US 20200135917A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Singh, Jagar, Ciavatti, Jerome
• Granted Patent: US 10,644,149 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.

Claims

1. A structure for a laterally-diffused metal-oxide-semiconductor field-effect transistor, the structure comprising:

a substrate;

a fin that projects from the substrate;

a channel region and a drain extension in a first section of the fin and the substrate beneath the first section of the fin;

a source region in the first section of the fin;

a drain region in a second section of the fin and the substrate beneath the second section of the fin;

a gate structure over the channel region in the first section of the fin;

a first trench isolation region arranged in the fin between the first section of the fin and the second section of the fin;

a dummy gate over a portion of the second section of the fin;

a second trench isolation region in the second section of the fin, the second trench isolation region laterally separated from the first trench isolation region by the portion of the second section of the fin; and

a contact region in the second section of the fin,

wherein the second trench isolation region is arranged between the contact region and the portion of the second section of the fin, the drain region and the source region have a first conductivity type, the channel region has a second conductivity type opposite from the first conductivity type, and the contact region has the second conductivity type.

5. The structure of claim 1 wherein the drain extension and the drain region are contiguous in the substrate along an interface beneath the first trench isolation region.

7. The structure of claim 1 wherein the fin has a height relative to the substrate, and the first trench isolation region penetrates through the height of the fin to terminate at an interface between the fin and the substrate.

8. The structure of claim 1 wherein the channel region contains a first dopant concentration, and the drain extension contains a second dopant concentration that is less than the first dopant concentration.

9. The structure of claim 1 wherein the gate structure is further arranged over the drain extension in the first section of the fin, and the gate structure has an overlapping arrangement with the first trench isolation region.

10. The structure of claim 9 wherein the gate structure is spaced apart from the dummy gate over the first trench isolation region by a gap to provide a non-contacting arrangement.

11. The structure of claim 9 wherein the drain extension and the drain region are contiguous along an interface in the substrate beneath the first trench isolation region.

14. The structure of claim 1 wherein the channel region contains a first semiconductor material with a first electrical resistivity, and the drain extension contains a second semiconductor material with a second electrical resistivity that is greater than the first electrical resistivity.

2-4. -4. (canceled)

6. A structure for a laterally-diffused metal-oxide-semiconductor field-effect transistor, the structure comprising:

a substrate;

a fin that projects from the substrate;

a channel region and a drain extension in a first section of the fin and the substrate beneath the first section of the fin;

a source region in the first section of the fin;

a drain region in a second section of the fin and the substrate beneath the second section of the fin;

a gate structure over the channel region in the first section of the fin;

a first trench isolation region arranged in the fin between the first section of the fin and the second section of the fin;

a dummy gate over a portion of the second section of the fin; and

a second trench isolation region in the second section of the fin, the second trench isolation region laterally separated from the first trench isolation region by the portion of the second section of the fin,

wherein the drain region and the source region have a first conductivity type, the channel region has a second conductivity type opposite from the first conductivity type, and

the drain region extends in the substrate beneath the first trench isolation region and the second trench isolation region.

21. The structure of claim 6 wherein the gate structure is further arranged over the drain extension in the first section of the fin, and the gate structure has an overlapping arrangement with the first trench isolation region.

22. The structure of claim 21 wherein the gate structure is spaced apart from the dummy gate over the first trench isolation region by a gap to provide a non-contacting arrangement.

23. The structure of claim 21 wherein the drain extension and the drain region are contiguous along an interface in the substrate beneath the first trench isolation region.

24. The structure of claim 6 wherein the fin has a height relative to the substrate, and the first trench isolation region penetrates through the height of the fin to terminate at an interface between the fin and the substrate.

25. The structure of claim 6 wherein the channel region contains a first dopant concentration, and the drain extension contains a second dopant concentration that is less than the first dopant concentration.

12. A structure for a laterally-diffused metal-oxide-semiconductor field-effect transistor, the structure comprising:

a substrate;

a fin that projects from the substrate;

a channel region and a drain extension in a first section of the fin and the substrate beneath the first section of the fin;

a source region in the first section of the fin;

a drain region in a second section of the fin and the substrate beneath the second section of the fin;

a gate structure over the channel region in the first section of the fin;

a trench isolation region arranged in the fin between the first section of the fin and the second section of the fin; and

a dummy gate over a portion of the second section of the fin,

wherein the drain region and the source region have a first conductivity type, the channel region has a second conductivity type opposite from the first conductivity type, and the drain extension and the drain region are contiguous along a first interface in the substrate beneath the trench isolation region.

26. The structure of claim 12 wherein the gate structure is further arranged over the drain extension in the first section of the fin, and the gate structure has an overlapping arrangement with the trench isolation region.

27. The structure of claim 26 wherein the gate structure is spaced apart from the dummy gate over the trench isolation region by a gap to provide a non-contacting arrangement.

28. The structure of claim 12 wherein the fin has a height relative to the substrate, and the first trench isolation region penetrates through the height of the fin to terminate at a second interface between the fin and the substrate.

29. The structure of claim 12 wherein the channel region contains a first dopant concentration, and the drain extension contains a second dopant concentration that is less than the first dopant concentration.

13. (canceled)

15-20. -20. (canceled)