METHOD OF FORMING A TOP EPITAXY SOURCE/DRAIN STRUCTURE FOR A VERTICAL TRANSISTOR

• US 20200135920A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kong, Dexin, Cheng, Kangguo, Mochizuki, Shogo
• Granted Patent: US 11,189,724 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a metal into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin;

forming a patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer on the metal and a topmost surface of the ILD material; and

performing an anneal at a temperature of less than 450°

C. to cause metal induced layer exchange between the metal and the doped semiconductor material that provides the doped amorphous semiconductor material layer, wherein the exchanged doped semiconductor material is crystalline and is in direct contact with the topmost surface of the semiconductor fin.

2. The method of claim 1, wherein the metal is composed of aluminum (Al), silver (Ag), gold (Au) or antimony (Sb).

3. The method of claim 1, wherein the forming the metal comprises:

depositing, at a temperature below 450°

C., a layer containing the metal in the opening and on the topmost surface of the ILD material; and

removing the layer containing the metal from the topmost surface of the ILD material.

4. The method of claim 1, wherein the membrane is composed of a dielectric material and has a thickness that is below 10 nm.

5. The method of claim 1, wherein the doped amorphous semiconductor material layer includes an n-type dopant and is composed of silicon, germanium, or a silicon germanium alloy.

6. The method of claim 1, wherein the doped amorphous semiconductor material layer includes a p-type dopant and is composed of silicon, germanium, or a silicon germanium alloy.

7. The method of claim 1, wherein the doped amorphous semiconductor material layer is formed utilizing an epitaxial growth process that is performed at a temperature below 450°

C.

8. The method of claim 1, wherein the temperature of the anneal is from 200°

C. to 400°

C., and the anneal is performed in an inert ambient.

9. The method of claim 1, wherein the anneal forms a layer of a metal/semiconductor mixture between the membrane and the exchanged metal.

10. The method of claim 1, wherein the exchanged doped semiconductor material has a different crystalline orientation than the topmost surface of the semiconductor fin.

11. The method of claim 1, further comprising removing the membrane and the exchanged metal after the anneal.

12. The method of claim 11, further comprising recessing, after the removal of the membrane and the exchanged metal, the exchanged doped semiconductor material below the topmost surface of the ILD material.

13. A semiconductor structure comprising:

a semiconductor fin extending upwards from a semiconductor mesa portion of a semiconductor substrate;

a bottom source/drain structure laterally surrounding, and directly contacting, the semiconductor mesa portion of the semiconductor substrate;

a bottom gate spacer laterally surrounding, and directly contacting, a bottom portion of the semiconductor fin;

a gate structure laterally surrounding, and directly contacting, a middle portion of the semiconductor fin;

a top gate spacer laterally surrounding, and directly contacting, a top portion of the semiconductor fin; and

a top source/drain structure located on a topmost surface of the semiconductor fin, wherein the top source/drain structure is composed of a doped semiconductor material that is crystalline and has a different crystalline orientation than the topmost surface of the semiconductor fin.

14. The semiconductor structure of claim 13, further comprising an interlayer dielectric (ILD) material laterally surrounding the gate structure and the top source/drain structure.

15. The semiconductor structure of claim 14, further comprising a dielectric material liner located between the gate structure and the ILD material, wherein the dielectric material liner has a topmost surface that is coplanar with a topmost surface of the ILD material.

16. The semiconductor structure of claim 14, wherein the topmost source/drain structure has a topmost surface that is recessed relative to the topmost surface of the ILD material.

17. The semiconductor structure of claim 14, wherein the topmost source/drain structure has a topmost surface that is coplanar relative to the topmost surface of the ILD material.

18. The semiconductor structure of claim 13, wherein the semiconductor substrate and the semiconductor mesa portion are of integral construction.

19. The semiconductor structure of claim 13, wherein a portion of the top source/drain structure extends onto a topmost surface of the top gate spacer.

20. The semiconductor structure of claim 13, wherein the top source/drain structure has tapered sidewalls, a bottom portion having a first width, and an upper portion having a second width that is greater than the first width.