MULTI-CHANNEL DEVICE TO IMPROVE TRANSISTOR SPEED

• US 20200135921A1
• Filed: 12/20/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, Hsin-Chih
• Granted Patent: US 11,349,025 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/783 comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET for thin film transistors H01L29/78612, H01L29/78696
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78639 : with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors

Abstract

In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.

Claims

1. A semiconductor device comprising:

a bulk oxide disposed over a semiconductor substrate;

a semiconductor region disposed over the bulk oxide;

a lower source region and a lower drain region, wherein the lower source region and the lower drain region are above and directly contact the bulk oxide and are laterally spaced apart by a lower portion of the semiconductor region;

an upper source region coupled to the lower source region and an upper drain region coupled to the lower drain region, wherein the upper source region is laterally spaced from the upper drain region by an upper portion of the semiconductor region, and wherein the upper source region and the upper drain region are vertically spaced from the lower source region and the lower drain region;

a gate oxide disposed over the upper portion of the semiconductor region;

a gate electrode disposed directly above the gate oxide, the gate electrode being coupled to the semiconductor substrate;

a first channel region within the lower portion of the semiconductor region, above the bulk oxide, and between the lower source region and the lower drain region; and

a second channel region within the upper portion of the semiconductor region, below the gate oxide, and between the upper source region and the upper drain region, wherein the second channel region is parallel to the first channel region.

2. The semiconductor device of claim 1, wherein the bulk oxide and the gate oxide have the same thickness and are made of the same material.

3. The semiconductor device of claim 1, wherein the lower source region and the upper source region are arranged on a first side of the semiconductor region, and wherein the lower drain region and the upper drain region are arranged on a second side of the semiconductor region, the second side laterally spaced from the first side.

4. The semiconductor device of claim 1, wherein the first and second channel regions have the same length.

5. The semiconductor device of claim 1, wherein the lower drain region and the upper source region are arranged on a first side of the semiconductor region and wherein the lower source region and the upper drain region are arranged on a second side of the semiconductor region, the second side laterally spaced from the first side.

6. The semiconductor device of claim 5, further comprising:

a first peripheral gate electrode arranged adjacent to the upper source region and the lower drain region and spaced from semiconductor region by a first peripheral gate oxide, wherein the first peripheral gate electrode is coupled to the gate electrode;

a second peripheral gate electrode arranged adjacent to the upper drain region and the lower source region and spaced from semiconductor region by a second peripheral gate oxide, wherein the second peripheral gate electrode is coupled to the gate electrode;

a third channel region within the semiconductor region beside the first peripheral gate oxide and between the upper source region and the lower drain region; and

a fourth channel region beside the second peripheral gate oxide and between the upper drain region and the lower source region, wherein the fourth channel region is parallel to the third channel region, and wherein the fourth channel region is perpendicular to the first channel region.

7. The semiconductor device of claim 6, wherein the first, second, third and fourth channel regions have the same length.

8. The semiconductor device of claim 6, wherein the bulk oxide, the gate oxide, the first peripheral gate oxide and the second peripheral gate oxide have the same thickness and are made of the same material.

9. The semiconductor device of claim 6, wherein the gate electrode, the first peripheral gate electrode, and the second peripheral gate electrode have a same thickness.

10. A semiconductor device comprising:

a bulk oxide disposed over a semiconductor substrate;

a semiconductor region disposed over the bulk oxide;

a lower source region and a lower drain region, wherein the lower source region and the lower drain region are above the bulk oxide and spaced apart by a lower portion of the semiconductor region;

a first channel region above the bulk oxide, within the lower portion of the semiconductor region, and laterally between the lower source region and the lower drain region;

a gate oxide disposed over an upper portion of the semiconductor region, wherein a second channel region is below the gate oxide and within the upper portion of the semiconductor region;

a gate electrode disposed directly above the gate oxide, the gate electrode being coupled to the semiconductor substrate;

an upper source region coupled to the lower source region, overlying the lower drain region, and vertically spaced from the lower drain region by a third channel region within the semiconductor region;

an upper drain region coupled to the lower drain region, overlying the lower source region, and vertically spaced from the lower source region by a fourth channel region within the semiconductor region, wherein the upper source region is laterally spaced from the upper drain region by the second channel region;

a first peripheral gate electrode arranged adjacent to the upper source region and the lower drain region and spaced from the third channel region by a first peripheral gate oxide, wherein the first peripheral gate electrode is coupled to the semiconductor substrate; and

a second peripheral gate electrode arranged adjacent to the upper drain region and the lower source region and spaced from the fourth channel region by a second peripheral gate oxide, wherein the second peripheral gate electrode is coupled to the semiconductor substrate.

11. The semiconductor device of claim 10, wherein the first, second, third, and fourth channel regions have the same length.

12. The semiconductor device of claim 10, wherein the bulk oxide, the gate oxide, the first peripheral gate oxide, and the second peripheral gate oxide have the same thickness and are made of the same material.

13. The semiconductor device of claim 10, wherein the semiconductor substrate, the gate electrode, the first peripheral gate electrode, and the second peripheral gate electrode are made of the same material.

14. The semiconductor device of claim 10, wherein dielectric layers electrically insulate the semiconductor substrate, the gate electrode, the first peripheral gate electrode, and the second peripheral gate electrode from one another.

15. A method of forming a semiconductor device, comprising:

providing a silicon-on-insulator substrate comprising a bulk oxide disposed over a semiconductor substrate and a semiconductor region disposed over the bulk oxide, wherein the semiconductor region has a first doping type;

forming a gate oxide layer over the semiconductor region;

forming a gate electrode layer over the gate oxide layer;

patterning the gate oxide layer and the gate electrode layer using a mask, leaving a gate oxide and gate electrode covering a first portion of the semiconductor region and leaving a second portion of the semiconductor region uncovered, wherein the semiconductor region comprises corner regions comprising a first upper corner region laterally spaced from a second upper corner region and a first lower corner region laterally spaced from a second lower corner region, and wherein the first and second lower corner regions are vertically spaced from the first and second upper corner regions by portions of the semiconductor region;

performing ion implantation to dope the corner regions of the semiconductor region such that the corner regions have a second doping type different than the first doping type, wherein performing the ion implantation forms an upper source region, an upper drain region, a lower drain region, and a lower source region, respectively arranged in the first upper corner region, the second upper corner region, the first lower corner region, and the second lower corner region;

coupling the lower source region and the upper source region to a source voltage line;

coupling the lower drain region and the upper drain region to a drain voltage line; and

coupling the semiconductor substrate and the gate electrode to a gate voltage line.

16. The method of claim 15, wherein the semiconductor region comprises:

peripheral portions at a first height above the bulk oxide; and

a protruding center portion between the peripheral portions, wherein the protruding center portion is at a second height larger than the first height.

17. The method of claim 16, wherein,

the corner regions are within the protruding center portion of the semiconductor region;

the first upper corner region overlies the second lower corner region; and

the second upper corner region overlies the first lower corner region.

18. The method of claim 15, wherein after growing the gate oxide layer, the gate oxide layer covers outer sidewalls and an upper surface of the semiconductor region.

19. The method of claim 18, wherein after patterning the gate oxide layer and the gate electrode layer, a first peripheral gate electrode and a second peripheral gate electrode remain and are arranged along outer sidewalls of the semiconductor region, wherein the first peripheral gate electrode and the second peripheral gate electrode are spaced from the semiconductor region respectively by a first peripheral gate oxide and a second peripheral gate oxide.

20. The method of claim 19, wherein,

the first upper corner region overlies the first lower corner region;

and

the second upper corner region overlies the second lower corner region.