SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20200135922A1
• Filed: 11/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Kuang-Hsiu, Tsai, Sung-Yuan, Tang, Chi-Hsuan, Yu, Chun-Wei, Wang, Yu-Ren
• Granted Patent: US 11,049,971 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate structure disposed on the substrate; and

an epitaxial structure disposed in the substrate, at one side of the gate structure, the epitaxial structure comprising a portion being protruding from a top surface of the substrate, the portion comprising a discontinuous sidewall, wherein a distance between a turning point on the discontinuous sidewall and the gate structure is a maximum distance between the epitaxial structure and the gate structure.

2. The semiconductor device according to claim 1, wherein the discontinuous sidewalls comprises a gradually shrinking portion and a gradually expanding portion, and the turning point is disposed between the gradually shrinking portion and the gradually expanding portion.

3. The semiconductor device according to claim 2, wherein the gradually expanding portion has thickness being greater than that of the gradually shrinking portion.

4. The semiconductor device according to claim 2, wherein the gradually expanding portion has a doped concentration being greater than that of the gradually shrinking portion.

5. The semiconductor device according to claim 2, wherein the gradually expanding portion is disposed on the gradually shrinking portion, and a width of the gradually expanding portion gradually expands upwardly.

6. The semiconductor device according to claim 5, wherein a width of the gradually shrinking portion gradually expanded downwardly.

7. The semiconductor device according to claim 2, wherein the gradually expanding portion comprises a suspended platform.

8. The semiconductor device according to claim 7, wherein the suspended platform comprises a uniform thickness.

9. The semiconductor device according to claim 1, wherein the maximum distance is adjacent to the top surface of the substrate.

10. The semiconductor device according to claim 1, wherein the gate structure comprises a spacer, the spacer surrounds a gate layer and comprises a tapered sidewall.

11. A semiconductor device, comprising:

a substrate;

a gate structure disposed on the substrate; and

an epitaxial structure disposed in the substrate, at one side of the gate structure, the epitaxial structure comprising a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, wherein a top surface of the second epitaxial layer has a first width greater than a second width of the bottom surface of the second epitaxial layer.

12. The semiconductor device according to claim 11, wherein the first epitaxial layer comprises a gradually shrinking portion being partially protruding from a top surface of the substrate, and a bottom surface of the gradually shrinking portion has a third width being greater than the second width and the first width.

13. The semiconductor device according to claim 12, wherein a top surface of the gradually shrinking portion also has the second width.

14. The semiconductor device according to claim 12, wherein a top surface of the gradually shrinking portion has a fourth width being smaller than the first width, the second width and the third width.

15. The semiconductor device according to claim 11, wherein a distance between the gate structure and a turning point between the first epitaxial layer and the second epitaxial layer is a maximum distance between the gate structure and the epitaxial structure.

16. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate; and

forming an epitaxial structure in the substrate, at one side of the gate structure, the epitaxial structure comprising a portion being protruding from a top surface of the substrate, the portion comprising a discontinuous sidewall, wherein a distance between a turning point on the discontinuous sidewall and the gate structure is a maximum distance between the epitaxial structure and the gate structure.

17. The method of forming a semiconductor device according to claim 16, wherein the forming of the epitaxial structure comprises:

forming a first epitaxial layer in the substrate, at the side of the gate structure, wherein the first epitaxial layer comprising a gradually shrinking portion being protruded from the top surface of the substrate;

forming a first deposition layer sandwiched between the gate structure and the first epitaxial layer, to expose a top surface of the first epitaxial layer; and

forming a second epitaxial layer from the top surface of the first epitaxial layer.

18. The method of forming a semiconductor device according to claim 17, wherein the forming of the first epitaxial layer comprises:

forming a second deposition layer covering the gate structure, the second deposition layer comprising a tapered sidewall; and

forming the first epitaxial layer in the substrate.

19. The method of forming a semiconductor device according to claim 18, wherein the forming of the first deposition layer further comprising:

after forming the second deposition layer, forming a material layer covering the gate structure and the first epitaxial layer; and

partially removing the material layer to expose the top surface of the first epitaxial layer, and forming the first deposition layer.

20. The method of forming a semiconductor device according to claim 18, further comprising:

completely removing the first deposition layer and the second deposition layer, to obtain the epitaxial structure.