METHOD FOR FORMING STRESSOR, SEMICONDUCTOR DEVICE HAVING STRESSOR, AND METHOD FOR FORMING THE SAME

• US 20200135926A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Che-Wei, LIN, Hao-Hsiung, PAN, Samuel C.
• Granted Patent: US 11,164,972 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

Claims

1. A semiconductor device, comprising:

a semiconductor fin protruding from a substrate;

a gate structure comparing a gate insulating layer and a gate electrode disposed over the semiconductor fin, wherein the gate insulating layer is disposed between the semiconductor fin and the gate electrode;

source and drain regions disposed on opposite sides of the gate structure over the semiconductor fin; and

a first stressor disposed on one side of the semiconductor fin under the gate structure, and

a second stressor disposed on another side of the semiconductor fin opposite to the first stressor with respect to the semiconductor fin and under the gate structure.

2. The semiconductor device of claim 1, wherein:

the first stressor comprises of a material selected from the group consisting of He, Ne, and Ga.

3. The semiconductor device of claim 1, wherein:

the first stressor is disposed in a first region under the gate structure that is adjacent to a region that is under a central region of the semiconductor fin.

4. The semiconductor device of claim 3, wherein:

the second stressor is disposed in a second region under the gate structure that is adjacent to the region that is under the central region of the semiconductor fin, wherein the second region is opposite of the first region with respect to the semiconductor fin.

5. The semiconductor device of claim 1, wherein:

the substrate is one selected from the group consisting of a Si substrate, a Ge substrate, a SiGe substrate, a GaAs substrate, and an InGaAs substrate.

6. The semiconductor device of claim 1, wherein:

the first and second stressors have a lattice constant that is greater than that of a region of the substrate immediately adjacent and between to the first and second stressors.

7. The semiconductor device of claim 1, wherein:

the first stressor and the second stressor have a concentration of material between 10¹⁵/cm3 to 10²⁰/cm3.

8. The semiconductor device of claim 1, wherein:

the second stressor comprises of a material selected from the group consisting of He, Ne, and Ga.

9. A semiconductor device, comprising:

a semiconductor fin disposed a substrate;

a gate structure comparing a gate insulating layer and a gate electrode disposed over the semiconductor fin;

a first stressor disposed on one side of the semiconductor fin under the gate structure, and

a second stressor disposed on another side of the semiconductor fin opposite to the first stressor with respect to the semiconductor fin and under the gate structure.

10. The semiconductor device of claim 9, wherein:

the first stressor and the second stressor have a concentration of material between 10¹⁰/cm3 to 10²⁰/cm3.

11. The semiconductor device of claim 9, wherein:

the second stressor comprises of a material selected from the group consisting of He, Ne, and Ga.

12. The semiconductor device of claim 9, wherein:

the substrate is one selected from the group consisting of a Si substrate, a Ge substrate, a SiGe substrate, a GaAs substrate, and an InGaAs substrate.

13. The semiconductor device of claim 9, wherein:

the first stressor is disposed in a first region under the gate structure that is adjacent to a region that is under a central region of the semiconductor fin.

14. The semiconductor device of claim 13, wherein:

the second stressor is disposed in a second region under the gate structure that is adjacent to the region that is under the central region of the semiconductor fin, wherein the second region is opposite of the first region with respect to the semiconductor fin.

15. A semiconductor device, comprising:

first and second stressors sequentially disposed in a substrate;

a first gate structure of a first transistor comprising a first gate insulating layer and a first gate electrode disposed over the first stressor;

a second gate structure of a second transistor comprising a second gate insulating layer and a second gate electrode disposed over the second stressor; and

first source and first drain regions of the first transistor disposed on opposite sides of the first gate structure and second source and second drain regions of the second transistor disposed on opposite sides of the second gate structure, wherein the first transistor and the second transistor are N-type transistors, or the first transistor and the second transistor are P-type transistors.

16. The semiconductor device of claim 15, wherein the substrate is one selected from the group consisting of a Si substrate, a Ge substrate, a SiGe substrate, a GaAs substrate, an InGaAs substrate, and a silicon-on-insulator substrate.

17. The semiconductor device of claim 15, further comprising:

a nanowire disposed on the substrate and over the first stressor.

18. The semiconductor device of claim 17, wherein the nanowire is an InAs nanowire.

19. The semiconductor device of claim 15, wherein the first stressor is disposed between the first source and first drain regions under the first gate structure.

20. The semiconductor device of claim 19, wherein the first stressor has a length of 10 nm along a direction between the first source and first drain regions.