FINFET WITH IMPROVED NITRIDE TO FIN SPACING

• US 20200135927A1
• Filed: 06/12/2018
• Published: 04/30/2020
• Est. Priority Date: 06/12/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: OK, Injo, Xie, Ruilong, Park, Chanro, Sung, Min Gyu
• Granted Patent: US 10,790,395 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device is described. The semiconductor device includes a dielectric layer oriented substantially parallelly to a substrate. The semiconductor device includes a metal layer formed on top of the dielectric layer. The semiconductor device includes a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer. The semiconductor device includes a gate insulator deposited on top of the fins and the dielectric layer. The semiconductor device includes an optical projection lithography (OPL) material deposited on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area. The semiconductor device includes a first exposed gate insulator area formed by removing the metal layer under the first exposed surface area. The semiconductor device includes a first exposed fin area formed by removing the gate insulator from the first exposed gate insulator area. The semiconductor device includes a substantially planar self-aligning gate cap filling a recess in the first exposed fin area and an adjacent area of the metal layer.

Claims

1. A semiconductor device comprising:

a dielectric layer oriented substantially parallelly to a substrate;

a metal layer formed on top of the dielectric layer;

a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer;

a gate insulator deposited on top of the fins and the dielectric layer;

an optical projection lithography (OPL) material deposited on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area;

a first exposed gate insulator area formed by removing the metal layer under the first exposed surface area;

a first exposed fin area formed by removing the gate insulator from the first exposed gate insulator area; and

a substantially planar self-aligning gate cap filling a recess in the first exposed fin area and an adjacent area of the metal layer.

2. The semiconductor device of claim 1, wherein the OPL material is removed prior to forming the substantially planar self-aligning gate cap.

3. The semiconductor device of claim 1, wherein the substantially planar self-aligning gate cap is formed by a deposition.

4. The semiconductor device of claim 1, wherein the top surface of the device is rendered substantially planar and excess gate cap material is removed by a planarization.

5. The semiconductor device of claim 1, wherein the recess in the first exposed fin area is formed by a fifth etching and the recess in an adjacent area of the metal layer is formed by a sixth etching.

6. The semiconductor device of claim 5, wherein the fifth etching comprises a dry etch process.

7. The semiconductor device of claim 5, wherein the fifth etching comprises a wet etch process.

8. The semiconductor device of claim 5, wherein the sixth etching comprises a wet etch process.

9. The semiconductor device of claim 5, wherein the sixth etching comprises a dry etch process.

10. A method comprising:

forming a dielectric layer oriented substantially parallelly to a substrate;

forming a metal layer formed on top of the dielectric layer;

forming a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer;

forming a gate insulator deposited on top of the fins and the dielectric layer;

depositing OPL material on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area;

first etching, following the depositing, the first exposed surface area, removing the metal layer under the first exposed surface area to form a first exposed gate insulator area;

second etching the first exposed gate insulator area, removing the gate insulator from the first exposed gate insulator area to form a first exposed fin area;

fourth etching, following the second etching, the device, creating a recess in the first exposed fin area and an adjacent area of the metal layer; and

forming, following the fourth etching, a substantially planar self-aligning gate cap filling the recess.

11. The method of claim 10, further comprising third etching, following the second etching and before the fourth etching, the device, removing the OPL material.

12. The method of claim 10, wherein the substantially planar self-aligning gate cap is formed by a deposition.

13. The method of claim 10, further comprising planarizing, following forming the self-aligning gate cap, the device, removing excess gate cap material.

14. The method of claim 10, wherein the fourth etching comprises a fifth etching configured to create a recess in the first exposed fin area and a sixth etching configured to create a recess in an adjacent area of the metal layer.

15. The method of claim 14, wherein the fifth etching comprises a dry etch process.

16. The method of claim 14, wherein the fifth etching comprises a wet etch process.

17. The method of claim 14, wherein the sixth etching comprises a wet etch process.

18. The method of claim 14, wherein the sixth etching comprises a dry etch process.

19. A semiconductor fabrication system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processors via the memories, the stored program instructions causing the fabrication system to perform operations comprising:

forming a dielectric layer oriented substantially parallelly to a substrate;

forming a metal layer formed on top of the dielectric layer;

forming a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer;

forming a gate insulator deposited on top of the fins and the dielectric layer;

depositing OPL material on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area;

first etching, following the depositing, the first exposed surface area, removing the metal layer under the first exposed surface area to form a first exposed gate insulator area;

second etching the first exposed gate insulator area, removing the gate insulator from the first exposed gate insulator area to form a first exposed fin area;

fourth etching, following the second etching, the device, creating a recess in the first exposed fin area and an adjacent area of the metal layer; and

forming, following the fourth etching, a substantially planar self-aligning gate cap filling the recess.

20. The semiconductor fabrication system of claim 19, further comprising third etching, following the second etching and before the fourth etching, the device, removing the OPL material.