SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20200135929A1
• Filed: 10/21/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: VAN DAL, Marcus Johannes Henricus, DOORNBOS, Gerben
• Granted Patent: US 11,264,506 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure including alternately stacked semiconductor layers and sacrificial layers;

forming a sacrificial gate structure over the stacked structure;

forming a dielectric layer over the sacrificial gate structure;

removing the sacrificial gate structure, thereby forming a gate space;

removing the sacrificial layers in the gate space, thereby releasing the semiconductor layers; and

forming a gate structure wrapping around the semiconductor layers,

wherein the semiconductor layers are made of an oxide semiconductor material.

2. The method of claim 1, wherein the oxide semiconductor material includes one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC)-IGZO, ZnO, In₂O₃, Ga₂O₃, and ZnON.

3. The method of claim 1, wherein the oxide semiconductor material includes amorphous indium gallium zinc oxide (IGZO).

4. The method of claim 1, wherein the sacrificial layer includes one selected from the group consisting of an insulating material, an amorphous or polycrystalline semiconductor material, and a metal nitride material.

5. The method of claim 2, wherein the stacked structure is formed over an insulating material layer.

6. The method of claim 5, wherein the insulating material layer covers transistors formed over a semiconductor substrate.

7. The method of claim 1, wherein the stacked structure is formed by:

alternately forming the semiconductor layers and the sacrificial layers on an insulating material layer; and

patterning the semiconductor layers and the sacrificial layers into one or more fin structures.

8. A method of manufacturing a semiconductor device, comprising:

forming a fin structure including alternately stacked semiconductor layers and sacrificial layers over a first dielectric layer;

forming a sacrificial gate structure over the fin structure;

forming gate sidewall spacers on opposing side faces of the sacrificial gate structure;

forming a second dielectric layer over the sacrificial gate structure and the fin structure;

removing the sacrificial gate structure, thereby forming a gate space;

removing the sacrificial layers in the gate space, thereby releasing channel regions of the semiconductor layers;

forming a gate structure wrapping around the channel regions of the semiconductor layers;

forming a third dielectric layer;

forming a contact opening in the third dielectric layer and the second dielectric layer;

removing the sacrificial layers in the contact opening, thereby releasing source/drain regions of the semiconductor layers; and

forming a source/drain contact wrapping around the source/drain regions of the semiconductor layers,

wherein the semiconductor layers are made of an oxide semiconductor material.

9. The method of claim 8, wherein the oxide semiconductor material includes one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC)-IGZO, ZnO, In₂O₃, Ga₂O₃, and ZnON.

10. The method of claim 8, wherein the oxide semiconductor material includes amorphous indium gallium zinc oxide (IGZO).

11. The method of claim 10, wherein the sacrificial layer includes one selected from the group consisting of as silicon oxide, silicon nitride, silicon oxynitride, SiOC, aluminum oxide, hafnium oxide.

12. The method of claim 10, wherein the sacrificial layer includes one selected from the group consisting of amorphous or polycrystalline Si, SiGe and Ge.

13. The method of claim 10, wherein the sacrificial layer includes one selected from the group consisting of TiN and TaN.

14. The method of claim 10, wherein the first dielectric layer covers transistors formed over a semiconductor substrate.

15. The method of claim 10, wherein:

in the removing the sacrificial layers in the contact opening, parts of the sacrificial layers remain, and

after the source/drain contact is formed, the remaining parts of the sacrificial layers are disposed between the source/drain contact and the gate structure.

16. A semiconductor device including a power switch circuit and a logic circuit, the power switch circuit comprising:

a first dielectric layer;

a thin film transistor (TFT) formed on the first dielectric layer, wherein;

the TFT includes;

semiconductor nano-sheets vertically arranged;

a gate dielectric layer wrapping around a channel region of each of the semiconductor nano-sheets;

a gate electrode layer formed on the gate dielectric layer, wherein the semiconductor nano-sheets are made of an oxide semiconductor material.

17. The semiconductor device of claim 16, wherein the oxide semiconductor material includes one selected from the group consisting of indium gallium zinc oxide (IGZO), c-axis aligned crystal (CAAC)-IGZO, ZnO, In2O3, Ga2O3, and ZnON.

18. The semiconductor device of claim 16, wherein the oxide semiconductor material includes amorphous indium gallium zinc oxide (IGZO).

19. The semiconductor device of claim 16, wherein:

a thickness T1 of each of the semiconductor nano-sheets is in a range from 5 nm to 30 nm, and

a width W1 of each of the semiconductor nano-sheets along a gate extending direction is in a range from 10 nm to 50 nm.

20. The semiconductor device of claim 19, wherein a ratio W1/T1 is in a range from 2 to 5.