CRYSTALLINE SEMICONDUCTOR LAYER FORMED IN BEOL PROCESSES

• US 20200135930A1
• Filed: 09/27/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Passlack, Matthias, Duriez, Blandine, Vellianitis, Georgios, Doornbos, Gerben, Van Dal, Marcus Johannes Henricus, Holland, Martin Christopher, Manfrini, Mauricio
• Granted Patent: US 10,991,576 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Claims

1. A structure, comprising:

a substrate;

a first dielectric layer over the substrate;

a crystalline second dielectric layer over the first dielectric layer; and

a first crystalline semiconductor layer over the crystalline second dielectric layer.

2. The structure of claim 1, wherein the first dielectric layer is an inter-metal dielectric layer.

3. The structure of claim 1, further comprising a metal layer between the crystalline second dielectric layer and the first dielectric layer.

4. The structure of claim 3, wherein the metal layer is coupled to an interconnect structure within the first dielectric layer.

5. The structure of claim 1, wherein the crystalline second dielectric layer is magnesium oxide.

6. The structure of claim 1, further comprising a second crystalline semiconductor layer between the first crystalline semiconductor layer and crystalline second dielectric layer.

7. The structure of claim 1, wherein the first crystalline semiconductor layer is a silicon layer.

8. The structure of claim 6, wherein the first crystalline semiconductor layer includes a different semiconductor material from that of the second crystalline semiconductor layer.

9. The structure of claim 1, further comprising a source/drain structure and a gate structure each positioned at least partially over the first crystalline semiconductor layer.

10. The structure of claim 1, further comprising an insulation structure laterally adjacent to the first crystalline semiconductor layer and over the first dielectric layer.

11. The structure of claim 1, further comprising a front-end-of-line semiconductor device positioned between the substrate and the first dielectric layer.

12. The structure of claim 1, wherein the first dielectric layer is amorphous.

13. A device, comprising:

a first dielectric layer;

a crystalline magnesium oxide layer over the first dielectric layer;

a crystalline semiconductor layer over the crystalline magnesium oxide layer;

a gate structure at least partially overlapping the crystalline semiconductor layer; and

a source/drain region contacting the crystalline semiconductor layer.

14. The device of claim 13, wherein the gate structure is positioned between the crystalline magnesium oxide layer and the first dielectric layer.

15. The device of claim 14, wherein the gate structure at least partially overlaps the source/drain region.

16. The device of claim 14, wherein the gate structure is coupled to an interconnect structure formed within the first dielectric layer.

17. The device of claim 13, wherein the gate structure is positioned at least partially over the crystalline semiconductor layer.

18. The device of claim 17, wherein the source/drain region includes a source/drain structure that is positioned at least partially over the crystalline semiconductor layer.

19. A method, comprising:

receiving a wafer, the wafer having a substrate and an amorphous dielectric layer over the substrate;

forming a crystalline dielectric layer over the amorphous dielectric layer;

depositing a layer of amorphous semiconductor material over the crystalline dielectric layer; and

crystalizing the amorphous semiconductor material through nanosecond laser annealing.

20. The method of claim 19, further comprising:

forming a metal layer over the amorphous dielectric layer; and

wherein the crystalline dielectric layer is formed over the metal layer.