TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS

• US 20200135931A1
• Filed: 05/31/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: QIAN, Haijiao, YANG, Chengshao, HUANG, Yinhu, WAN, Yunhai
• Granted Patent: US 10,923,597 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.

Claims

1. A transistor, comprising:

a substrate;

an active region provided on the substrate and comprising a polycrystalline silicon region;

an etch stop layer provided at a side of the polycrystalline silicon region distal to the substrate; and

a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both provided at a side of the etch stop layer distal to the substrate;

wherein the polycrystalline silicon region has a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; and

an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer, and an orthographic projection, on the plane in which the lower surface of the etch stop layer lies, of at least one of the first side surface and the second side surface of the polycrystalline silicon region is located within the lower surface of the etch stop layer.

2. The transistor according to claim 1, wherein the orthographic projection of the polycrystalline silicon region on the plane in which the lower surface of the etch stop layer lies is entirely located within the lower surface of the etch stop layer.

3. The transistor according to claim 1, wherein the active region further comprises a first amorphous silicon region and a second amorphous silicon region which are provided in the same layer as the polycrystalline silicon region, and the first amorphous silicon region and the second amorphous silicon region are connected to the first side surface and the second side surface of the polycrystalline silicon region, respectively.

4. The transistor according to claim 3, wherein the first heavily doped amorphous silicon region is provided at a side of the first amorphous silicon region distal to the substrate, and the second heavily doped amorphous silicon region is provided at a side of the second amorphous silicon region distal to the substrate.

5. The transistor according to claim 3, further comprising a third amorphous silicon region provided at a side of the first amorphous silicon region distal to the substrate, and a fourth amorphous silicon region provided at a side of the second amorphous silicon region distal to the substrate.

6. The transistor according to claim 5, wherein the first heavily doped amorphous silicon region is provided at a side of the third amorphous silicon region distal to the substrate, and the second heavily doped amorphous silicon region is provided at a side of the fourth amorphous silicon region distal to the substrate.

7. The transistor according to claim 1, further comprising a gate provided on an upper surface of the substrate.

8. The transistor according to claim 7, further comprising a gate insulation layer provided at a side of the gate distal to the substrate.

9. The transistor according to claim 1, further comprising a first electrode provided at a side of the first heavily doped amorphous silicon region distal to the substrate, and a second electrode provided at a side of the second heavily doped amorphous silicon region distal to the substrate.

10. A display substrate, comprising the transistor according to claim 1 and a pixel electrode coupled to the transistor.

11. A display apparatus, comprising the display substrate according to claim 10 and a counter substrate provided opposite to the display substrate.

12. A method for manufacturing a transistor, comprising:

providing a substrate;

forming a first amorphous silicon layer on the substrate, and converting a part of the first amorphous silicon layer into a polycrystalline silicon region;

forming an etch stop layer on the first amorphous silicon layer by a patterning process; and

forming a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region on the etch stop layer, the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region;

wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer, and an orthographic projection, on the plane in which the lower surface of the etch stop layer lies, of at least one of the first side surface and the second side surface of the polycrystalline silicon region is located within the lower surface of the etch stop layer.

13. The method according to claim 12, wherein the orthographic projection of the polycrystalline silicon region on the plane in which the lower surface of the etch stop layer lies is located within the lower surface of the etch stop layer.

14. The method according to claim 12, wherein the forming the first amorphous silicon layer on the substrate comprises:

forming a first amorphous silicon region and a second amorphous silicon region, wherein the first amorphous silicon region and the second amorphous silicon region are connected to the first side surface and the second side surface of the polycrystalline silicon region, respectively.

15. The method according to claim 14, further comprising:

forming a third amorphous silicon region and a fourth amorphous silicon region on the first amorphous silicon region and the second amorphous silicon region, respectively.

16. The method according to claim 12, further comprising:

forming a gate on an upper surface of the substrate by a patterning process.

17. The method according to claim 12, wherein forming the first heavily doped amorphous silicon region and the second heavily doped amorphous silicon region on the etch stop layer comprises:

depositing a heavily doped second amorphous silicon layer on the etch stop layer, wherein the second amorphous silicon layer is used for forming the first heavily doped amorphous silicon region and the second heavily doped amorphous silicon region.

18. The method according to claim 17, after forming the second amorphous silicon layer, further comprising:

forming a conduction layer on the second amorphous silicon layer, wherein the conduction layer is used for forming a first electrode and a second electrode.

19. The method according to claim 18, after forming the conduction layer, further comprising:

etching the conduction layer and the second amorphous silicon layer by using one photolithography process to form the first electrode and the second electrode, and the first heavily doped amorphous silicon region and the second heavily doped amorphous silicon region.

20. The method according to claim 14, wherein forming the first amorphous silicon region and the second amorphous silicon region comprises:

etching the first amorphous silicon layer by using one photolithography process to form the first amorphous silicon region and the second amorphous silicon region.