SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
First Claim
1. A gate-all-around semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:
- semiconductor wires disposed and vertically arranged over a substrate, the semiconductor wires having channel regions, source regions and drain regions, respectively;
a gate dielectric layer wrapping around each of the channel regions of the semiconductor wires;
a gate electrode layer disposed on the gate dielectric layer; and
a source epitaxial layer wrapping around each of the source regions of the semiconductor wires and a drain epitaxial layer wrapping around each of the drain regions of the semiconductor wires, wherein;
the semiconductor wires are made of a first semiconductor material and the source epitaxial layer and the drain epitaxial layer are made of a second semiconductor material different from the first semiconductor material, anda thickness and a width of each of the source regions and each of the drain regions of the semiconductor wires are smaller than a thickness and a width of each of the channel regions of the semiconductor wires.
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Accused Products
Abstract
A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.
1 Citation
20 Claims
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1. A gate-all-around semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:
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semiconductor wires disposed and vertically arranged over a substrate, the semiconductor wires having channel regions, source regions and drain regions, respectively; a gate dielectric layer wrapping around each of the channel regions of the semiconductor wires; a gate electrode layer disposed on the gate dielectric layer; and a source epitaxial layer wrapping around each of the source regions of the semiconductor wires and a drain epitaxial layer wrapping around each of the drain regions of the semiconductor wires, wherein; the semiconductor wires are made of a first semiconductor material and the source epitaxial layer and the drain epitaxial layer are made of a second semiconductor material different from the first semiconductor material, and a thickness and a width of each of the source regions and each of the drain regions of the semiconductor wires are smaller than a thickness and a width of each of the channel regions of the semiconductor wires. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device, comprising:
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first semiconductor wires made of a first semiconductor material and vertically arranged over a substrate, the semiconductor wires having channel regions and source/drain regions, respectively; second semiconductor wires made of a second semiconductor material different from the first semiconductor material and each disposed between and connecting adjacent ones of the channel regions of the first semiconductor wires, the channel regions of the first semiconductor wires and the second semiconductor wires forming a channel layer; a gate dielectric layer disposed channel layer; a gate electrode layer disposed on the gate dielectric layer; and a source/drain epitaxial layer wrapping around each of the source/drain regions of the first semiconductor wires, wherein; a thickness and a width of each of the source/drain regions of the first semiconductor wires are smaller than a thickness and a width of each of the channel regions of the first semiconductor wires. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device, comprising:
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first semiconductor wires made of a first semiconductor material and vertically arranged over a substrate, the semiconductor wires having channel regions and source/drain regions, respectively; second semiconductor wires made of a second semiconductor material different from the first semiconductor material and each disposed between and connecting adjacent ones of the channel regions of the first semiconductor wires, the channel regions of the first semiconductor wires and the second semiconductor wires forming a first channel layer; third semiconductor wires made of a third semiconductor material, and vertically arranged over the substrate, the third semiconductor wires having channel regions, source regions and drain regions, respectively; a gate dielectric layer disposed channel layer and wrapping around the channel regions of the third semiconductor wires; a gate electrode layer disposed on the gate dielectric layer and over the channel layer and the channel regions of the third semiconductor wires; a first source/drain epitaxial layer wrapping around each of the source/drain regions of the first semiconductor wires; and a second source/drain epitaxial layer wrapping around each of the source/drain regions of the third semiconductor wires, wherein; a thickness and a width of each of the source/drain regions of the first semiconductor wires are smaller than a thickness and a width of each of the channel regions of the first semiconductor wires, and a thickness and a width of each of the source/drain regions of the third semiconductor wires are smaller than a thickness and a width of each of the channel regions of the third semiconductor wires. - View Dependent Claims (20)
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Specification