ARRAY SUBSTRATE INCLUDING A SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

• US 20200135935A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 09/30/2019
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: YUAN, Yong
• Granted Patent: US 11,189,732 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An array substrate includes a substrate, a first thin film transistor, and a second thin film transistor, and the first thin film transistor and the second thin film transistor each are located on a same side of the substrate. The first thin film transistor includes a first active layer being a polysilicon layer, and the second thin film transistor includes a second active layer being an oxide semiconductor layer and includes a first contact layer and a second contact layer. The first contact layer is located between the substrate and the second active layer, the second contact layer is located on a side of the second active layer facing away from the substrate, the first contact layer and the second contact layer each are in contact with the second active layer, and the second active layer, the first contact layer, and the second contact layer each are island-shaped.

Claims

1. An array substrate, comprising:

a substrate, a first thin film transistor, and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are located on a same side of the substrate;

wherein the first thin film transistor comprises a first active layer, the first active layer is a polysilicon layer, the second thin film transistor comprises a second active layer, the second active layer is an oxide semiconductor layer, and the second thin film transistor further comprises a first contact layer and a second contact layer, and

wherein the first contact layer is located between the substrate and the second active layer, the second contact layer is located on a side of the second active layer facing away from the substrate, the first contact layer and the second contact layer each are in contact with the second active layer, and the second active layer, the first contact layer, and the second contact layer each are island-shaped.

2. The array substrate of claim 1, wherein the first contact layer and the second contact layer each are made of a material of silicon oxide.

3. The array substrate of claim 1, further comprising:

an isolation layer, which is formed in a manner of atomic layer deposition;

wherein the isolation layer is located between the first contact layer and the substrate, or the isolation layer is located on a side of the second contact layer facing away from the substrate, or the isolation layer comprises a portion located between the first contact layer and the substrate and a portion located on a side of the second contact layer facing away from the substrate;

wherein the isolation layer overlaps the second thin film transistor.

4. The array substrate of claim 3, wherein a material of the isolation layer comprises alumina.

5. The array substrate of claim 3, wherein the isolation layer comprises a first isolation layer and a second isolation layer, wherein the first isolation layer is located between the first contact layer and the substrate, and the second isolation layer is located on the side of the second contact layer facing away from the substrate;

and

the first isolation layer comprises a first portion, the second isolation layer comprises a second portion, and the first portion is in contact with the second portion; and

the first portion and the second portion are located at least in a region between the first thin film transistor and the second thin film transistor.

6. The array substrate of claim 5, wherein in a plane parallel to the substrate, the first portion and the second portion each surround the second active layer, the first contact layer, and the second contact layer.

7. The array substrate of claim 5, wherein the first thin film transistor further comprises a buffer layer, a first gate insulating layer, a first gate, a first interlayer insulating layer, a first source, and a first drain;

the buffer layer is located between the substrate and the first active layer, the first gate insulating layer is located on a side of the first active layer facing away from the substrate, the first gate is located on a side of the first gate insulating layer facing away from the substrate, the first interlayer insulating layer is located on a side of the first gate facing away from the substrate, the first source and the first drain each are located on a side of the first interlayer insulating layer facing away from the substrate, and the first source and the first drain are separately connected to the first active layer; and

the first isolation layer extends from a region where the second thin film transistor is located to a region where the first thin film transistor is located, and forms the first interlayer insulating layer.

8. The array substrate of claim 7, wherein the buffer layer and the first gate insulating layer each do not overlap the second active layer, the first contact layer, and the second contact layer.

9. The array substrate of claim 7, wherein the first gate insulating layer comprises a silicon nitride layer.

10. The array substrate of claim 9, wherein the isolation layer further comprises a third isolation layer, the third isolation layer is located between the substrate and the second thin film transistor and extends from the region where the second thin film transistor is located to the region where the first thin film transistor is located, and a portion of the third isolation layer extending to the region where the first thin film transistor is located is located between the substrate and the buffer layer;

and

the third isolation layer comprises a third portion, and in the region between the first thin film transistor and the second thin film transistor, the third portion is in contact with the first portion.

11. The array substrate of claim 7, further comprising:

a first insulating layer and a second insulating layer;

wherein the first insulating layer is located on the side of the first interlayer insulating layer facing away from the substrate, and the second insulating layer is located on a side of the first insulating layer facing away from the substrate;

wherein the first insulating layer and the first contact layer are made of a same material, or the first insulating layer and the second contact layer are made of a same material; and

wherein the second isolation layer extends from the region where the second thin film transistor is located to the region where the first thin film transistor is located, and forms the second insulating layer.

12. The array substrate of claim 5, further comprising:

a third insulating layer, which extends from a region where the first thin film transistor is located to a region where the second thin film transistor is located, and the third insulating layer is made of an organic material;

wherein the first thin film transistor further comprises a first source and a first drain, the first source and the first drain being separately connected to the first active layer;

wherein the second thin film transistor further comprises a second source and a second drain, the second source and the second drain being separately connected to the second active layer;

wherein the first source, the first drain, the second source, and the second drain are disposed at a same layer, made of a same material, and located on a side of the first active layer and the second active layer facing away from the substrate; and

wherein the third insulating layer is located between a film layer where the first source, the first drain, the second source and the second drain are located and a film layer where the second isolation layer is located.

13. The array substrate of claim 5, wherein the first thin film transistor further comprises a buffer layer, a first gate insulating layer, a first gate, a first interlayer insulating layer, a first source, a first drain, and a fourth insulating layer;

the buffer layer is located between the substrate and the first active layer, the first gate insulating layer is located on a side of the first active layer facing away from the substrate, the first gate is located on a side of the first gate insulating layer facing away from the substrate, the first interlayer insulating layer is located on a side of the first gate facing away from the substrate, the first source and the first drain each are located on a side of the first interlayer insulating layer facing away from the substrate, and the fourth insulating layer is located between a film layer where the first source and the first drain are located and the first interlayer insulating layer;

the first source and the first drain are separately connected to the first active layer; and

the second isolation layer extends from a region where the second thin film transistor is located to a region where the first thin film transistor is located and forms the fourth insulating layer in the region where the first thin film transistor is located.

14. The array substrate of claim 13, wherein the second thin film transistor further comprises a second gate and a third gate, the second gate is located between the substrate and the first contact layer, and the third gate is located on a side of the second contact layer facing away from the second active layer.

15. The array substrate of claim 5, wherein the first thin film transistor further comprises a first source and a first drain, the second thin film transistor further comprises a second source and a second drain, wherein the first source, the first drain, the second source, and the second drain are disposed at a same layer, made of a same material, and located on a side of the first active layer and the second active layer facing away from the substrate;

the second isolation layer extends from a region where the second thin film transistor is located to a region where the first thin film transistor is located and forms a second insulating layer, wherein the second insulating layer is located between a film layer where the first source and the first drain are located and the first active layer;

each of the first source and the first drain is connected to the first active layer through a respective one of a plurality of via holes of the second insulating layer; and

the second thin film transistor further comprises a second source connection portion and a second drain connection portion, wherein the second source connection portion and the second drain connection portion each are located between the second contact layer and the second isolation layer, the second source is connected to the second active layer through the second source connection portion, and the second drain is connected to the second active layer through the second drain connection portion.

16. The array substrate of claim 5, wherein the first thin film transistor further comprises a first source and a first drain, the second thin film transistor further comprises a second source and a second drain, wherein the first source, the first drain, the second source, and the second drain are disposed at a same layer, made of a same material, and located on a side of the first active layer and the second active layer facing away from the substrate;

the second isolation layer extends from a region where the second thin film transistor is located to a region where the first thin film transistor is located and forms a fourth insulating layer, wherein the fourth insulating layer is located between a film layer where the first source and the first drain are located and the first active layer;

each of the second source and the second drain is connected to the second active layer through a respective one of a plurality of via holes of the second isolation layer; and

the first thin film transistor further comprises a first source connection portion and a first drain connection portion, wherein the first source connection portion and the first drain connection portion each are located between the fourth insulating layer and the first active layer, the first source is connected to the first active layer through the first source connection portion, and the first drain is connected to the first active layer through the first drain connection portion.

17. A display panel, comprising:

an array substrate, a planarization layer and a light-emitting element layer, wherein the planarization layer is located between the array substrate and the light-emitting element layer;

wherein the array substrate, comprising;

a substrate, a first thin film transistor, and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are located on a same side of the substrate; and

wherein the first thin film transistor comprises a first active layer, the first active layer is a polysilicon layer, the second thin film transistor comprises a second active layer, the second active layer is an oxide semiconductor layer, and the second thin film transistor further comprises a first contact layer and a second contact layer, wherein the first contact layer is located between the substrate and the second active layer, the second contact layer is located on a side of the second active layer facing away from the substrate, the first contact layer and the second contact layer each are in contact with the second active layer, and the second active layer, the first contact layer, and the second contact layer each are island-shaped.

18. A display device, comprising the display panel of claim 17.

19. A manufacturing method of an array substrate, comprising:

providing a substrate;

forming a first active layer on the substrate, wherein the first active layer is an active layer of a first thin film transistor and is a polysilicon layer;

forming a first contact layer on the substrate;

forming a second active layer on the first contact layer, wherein the second active layer is an active layer of a second thin film transistor and is an oxide semiconductor layer; and

forming a second contact layer on the second active layer; and

wherein the first contact layer and the second contact layer each are in contact with the second active layer, and the second active layer, the first contact layer, and the second contact layer each are island-shaped.

20. The manufacturing method of claim 19, wherein the forming a first contact layer on the substrate further comprises:

forming a first isolation layer on the substrate in a manner of atomic layer deposition; and

forming the first contact layer on the first isolation layer; and

the forming a second contact layer on the second active layer further comprises;

forming a second isolation layer on the second contact layer in the manner of atomic layer deposition; and

wherein a portion of the first isolation layer and a portion of the second isolation layer which are beyond the second active layer, the first contact layer, and the second contact layer comprise portions that are in contact with each other.