METHOD OF PREVENTING CONTAMINATION OF LED DIE
1. A method comprising:
- (a) providing a wafer comprising an epitaxy layer and a dielectric layer with openings having metal contacts;
(b) depositing a barrier layer on the metal contacts and the dielectric layer;
(c) depositing a patterned photoresistive layer on the barrier layer in regions of the wafer overlaying the metal contact;
(d) depositing a reflective layer on the patterned photoresistive layer and the barrier layer; and
(e) removing the patterned photoresistive layer including portions of the reflective layer overlaying the patterned photoresistive layer.
A method for allowing a reflective layer to abut against an edge of a metal contact while preventing contamination of a metal contact for an LED die is provided. The method includes encapsulating an electrical contact (i.e. metal contact) via with a barrier layer prior to deposition of a reflective film layer. The barrier layer encapsulates the metal contact by defining a mask pattern with a larger size than the metal contact via, which prevents the metal contact from becoming contaminated by the reflective film. This encapsulation reduces contamination of the metal contact and also reduces the voltage drop during operation of the LED die.
- 1. A method comprising:
(a) providing a wafer comprising an epitaxy layer and a dielectric layer with openings having metal contacts; (b) depositing a barrier layer on the metal contacts and the dielectric layer; (c) depositing a patterned photoresistive layer on the barrier layer in regions of the wafer overlaying the metal contact; (d) depositing a reflective layer on the patterned photoresistive layer and the barrier layer; and (e) removing the patterned photoresistive layer including portions of the reflective layer overlaying the patterned photoresistive layer.
This application is a continuation U.S. patent application Ser. No. 15/842,391, filed Dec. 14, 2017, which is/are incorporated by reference as if fully set forth.
The present invention generally relates to light emitting diodes (LEDs), and more particularly relates to minimizing contamination during processing of LEDs.
Applications including varying LED die architectures are known. Vias are created in areas of LED arrangements where electrical contact is desired. It is understood by those of ordinary skill in the art that mobile atoms such as silver (Ag) and aluminum (Al) can migrate or otherwise relocate into vias during deposition or in subsequent processing steps.
This is particularly a problem in certain LED dies because Ag is known to contaminate the underlying epitaxy. The typical method for preventing contamination is to provide a barrier layer (or dielectric layer 114 as shown in
Producing LED dies typically involves multiple rounds of masking and photolithography, which requires a large via size in the second deposition layer to provide a margin for issues resulting from via misalignment. This mismatch in the size of vias between the first and second deposition layers defines the size of a critical dimension (CD) and if etching is used to form the via, this results in a large undercut, causing an enlarged CD.
Etching for semiconductor materials is well known, and is described in U.S. Pat. No. 9,583,353, which is incorporated by reference as if fully set forth herein. Applications including wafer bonding for LED architecture are also well known. One other known type of LED die is disclosed in U.S. Pat. No. 8,154,042, which is incorporated by reference as if fully set forth herein. These known types of devices have produced significant increases in light output. However, there are still contamination issues.
The reflective layer in LED dies contaminates the associated metal contact in a variety of ways. Contamination can occur due to direct deposition on top of contact metal, the reflective film anneal process, incursion of etch products in contact with the via during the etch process of the reflective layer, and/or voiding in a subsequent bonding layer due to removal of material from the first barrier layer during formation of the reflective layer. If trace elements of reflective film come into electrical contact with the underlying epitaxy, then a consistent high forward voltage can result.
It would be desirable to provide a reliable method of preventing contamination of the metal contacts in an LED die.
Briefly stated, a method for preventing contamination at a metal contact for an LED die is provided.
The present disclosure provides methods of applying a barrier layer to encapsulate the electrical contact (i.e. metal contact) which minimizes the critical dimension (CD) in the reflective layer, thereby increasing the total reflective surface on the LED die. The barrier layer encapsulates the metal contact by defining a mask pattern with a larger size than the metal contact via, which prevents the metal contact from becoming contaminated by the reflective film. This encapsulation prevents contamination of the metal contact and also reduces the voltage increase during operation of the LED die.
The foregoing Summary as well as the following Detailed Description will be best understood when read in conjunction with the appended drawings. In the drawings:
It is to be understood that the figures and descriptions for preventing contamination in an LED die have been simplified to illustrate elements that are relevant for a clear understanding, while eliminating, for the purpose of clarity, many other elements found in typical electronics packaging. Those of ordinary skill in the art may recognize that other elements and/or steps are desirable and/or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein.
During the etch removal process of LED die formation, the reflective layer is etched away from the metal contact via, and an over-etch process is used to ensure thorough removal of reflective film from metal contact via to prevent contamination. This etch removal process excessively reduces the total area of the mirror total reflective area and reduces the light output of the LED die. The embodiments disclosed herein eliminate the reflective film etch process with a more precisely controllable barrier layer dimension that reduces the light output lost due to the loss of the reflective area. In existing applications, a first barrier layer, which is removed partially or fully by the reflective film etch process, changes the die topography and causes large voids beneath the metal contact via after the wafer bonding process. The embodiments disclosed herein improve the die topography by eliminating the reflective film etch process and reduces the voids significantly.
A gap typically exists between the second barrier layer and the reflective film in LED dies due to over-etching of the reflective film layer. Mirror mask misalignment can result in the reflective film sitting directly on top of contact metal, and a subsequent thermal process both accelerates cross contamination and causes forward voltage to increase in an uncontrollable manner. The embodiments disclosed herein provide a design for LED dies with a sufficiently large barrier size to fully encapsulate the metal contact via, which eliminates reflective film from contaminating the metal contact. Embodiments disclosed herein deposit a blanket sheet of reflective mirror layer to maximize the mirror area and improve light output.
Production of an LED die includes multiples steps, which are illustrated in
During step 120 shown in
As shown in
During removal of the reflective film layer 152 from the top surface of the metal contact vias, partial etching of the first barrier layer 134 causes problems. Trace amounts of the reflective film layer 152 may enter the via during the formation and annealing steps, which causes an increase in the operating voltage of the LED device. Etching by-products are also generated during the etching of the reflective film layer 152, which may also cause an increase in the operating voltage of the device. Additionally, as the reflective film layer 152 is etched away from the metal contact region, material is removed from underneath the resist 162, causing a reduction in the total area of reflective film and causes a correlated reduction in light output of the LED die. The guard sheet (i.e. the second barrier layer 172) creates a region of low reflectivity between the top edge of the dielectric via and an outer edge of the guard sheet and a region of even lower reflectivity between the outer edge of the guard sheet and an inner edge of the reflective film. The first barrier layer 134, which is removed partially or fully by the reflective film etch process, changes the topography of the die, and can lead to large voids beneath the metal contact via after the wafer bonding process. Finally, during the masking process to enable etching away of the reflective film layer 152 from the metal contact via, any gross mask misalignment can cause the reflective film to be positioned on top of the metal contact 132, which is undesirable and leads to contamination of the metal contact 132. This issue is best illustrated by the right half side of
As disclosed generally herein, a barrier layer is provided to separate patterned islands of metal contact and a blanket sheet of a reflective mirror. The barrier layer enables contamination-free metal contact, which lowers the contact resistance and reduces the voltage drop and power consumption during LED die operation. In an embodiment, blanket sheets of reflective mirror layers, which are not partially etched away from the top of metal contact, are provided. This configuration improves the light output of LED die by maximizing the mirror area.
In an embodiment, the reflective film etching process is eliminated, which prevents mirror area loss and minimizes the light output loss. The LED die architecture disclosed herein improves the bottom contact surface topography while also significantly reducing the bonding void after the wafer bonding process. The finished LED die produced according to the embodiments disclosed herein provides improved performance by avoiding operating voltage increase, lowering power consumption, and increasing light output.
The barrier layer disclosed herein encapsulates the metal contact by providing a pattern with a larger diameter than a specific island of metal contact, hence preventing the metal contact from getting contaminated by the reflective mirror during processing or normal operation. By using formation steps and processes that allow the reflective mirror layer to be positioned directly adjacent to the guard sheet (i.e. in abutting contact) while preventing contamination of the contacts during processing and/or normal operation, light output is maximized and the operating voltage is minimized. This arrangement provides improved topography of the contact layer for LED die architectures which use submount bonding (e.g., vertical LED devices). In an embodiment, the method of forming the LED die disclosed herein provides a surface roughness reduction of approximately 20% compared to known LED dies. In an embodiment, the method of forming the LED die disclosed herein provides a surface roughness reduction of approximately 18.6% compared to known LED dies. Across the contact area, an RMS of approximately 60.0 nm is provided in known LED dies. According to an embodiment of a method disclosed herein, an RMS of less than 50.0 nm is provided. In an embodiment, an RMS of 48.8 nm is provided. As used herein, RMS is defined per ASME B46.1 as the root mean square average of the profile height deviations from the mean line.
In an embodiment, a method is provided for minimizing the offset incurred between the thin films for a mirror layer and a guard sheet which lie adjacent to each other on the dielectric layers during the formation of the electrical contact. The method includes forming a via in the dielectric layer. This step can include the formation of the via through any material present on the semiconductor prior to dielectric film deposition such that the semiconductor can be connected electrically to the external environment through the via. The method includes forming an electrical contact on the semiconductor through the via using a single layer or multiple layers of thin films. In an embodiment, the method includes forming a guard sheet (i.e. barrier layer) over the via as a cap or shield to prevent incursion of contaminants into the via. The method includes forming a reflective layer on the dielectric and achieving tight CD control between the reflective layer and guard sheet.
As shown in
The term “patterning” or “patterned” with respect to the photoresistive layers used herein can be performed according to a variety of methods. In an embodiment, the patterning is performed by lift-off. In another embodiment, the patterning is performed by wet-etching.
This table highlights the importance of controlling the size of the CD over the oxide via to balance between maximizing flux with no penalty in forward voltage. Where this would not have been possible in an embodiment where the Ag was etched back from the via to 8 μm, as tighter CD margins would not be feasible in production and large over-etch margins are designed into the product to prevent epi poisoning, this embodiment shows that the CD size can be significantly reduced, thereby improving total reflectance and die flux levels.
As shown in
An additional embodiment for forming an LED die 800 is disclosed in
In an embodiment shown in
One of ordinary skill in the art would recognize from the present embodiments that the method and configuration described herein can be applied to any LED architecture. In particular, the methods and configurations described herein can be applied to any LED architecture that uses metal contact and a reflective layer.
The present embodiments can be implemented using standard manufacturing equipment according to known wafer fabrication assemblies and methods. The present embodiments can be incorporated into a modified flow of existing manufacturing process in wafer fabrication to enable the die architecture change.
The non-limiting methods and embodiments described herein for an LED die may be modified for a variety of applications and uses while remaining within the spirit and scope of the claims. The implementations and variations described herein, and/or shown in the drawings, are presented by way of example only and are not limiting as to the scope and spirit. The descriptions herein may be applicable to all implementations of the method and system described herein although it may be described with respect to a particular implementation.
As described herein, the methods described herein are not limited to any particular element(s) that perform(s) any particular function(s) and some steps of the methods presented need not necessarily occur in the order shown. For example, in some cases two or more method steps may occur in a different order or simultaneously. In addition, some steps of the described methods may be optional (even if not explicitly stated to be optional) and, therefore, may be omitted. These and other variations of the methods disclosed herein will be readily apparent, especially in view of the description of the method for using sputtering deposition to grow layers in light emitting devices described herein, and are considered to be within the full scope of the invention.
Some features of some implementations may be omitted or implemented with other implementations. The device elements and method elements described herein may be interchangeable and used in or omitted from any of the examples or implementations described herein. Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements.