SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20200136014A1
• Filed: 11/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Hui-Lin, Hsu, Chia-Chang, Weng, Chen-Yi, Hsieh, Chin-Yang, Jhang, Jing-Yin
• Granted Patent: US 10,840,432 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 41/307 insulating or semiconductive spacer
• CPC Class Codes: H01F 41/34 in patterns, e.g. by lithography
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the t op electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

Claims

1. A method for fabricating semiconductor device, comprising:

forming an inter-metal dielectric (IMD) layer on a substrate;

forming a metal interconnection in the IMD layer;

forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration;

forming a free layer on the bottom electrode layer;

forming a top electrode layer on the free layer; and

patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

2. The method of claim 1, further comprising:

forming a patterned mask on the bottom electrode layer;

removing part of the bottom electrode layer and part of the IMD layer to form a trench;

forming the free layer on the bottom electrode layer and into the trench;

forming the top electrode layer on the free layer; and

patterning the top electrode layer, the free layer, and the bottom electrode layer to form the MTJ and an alignment mark adjacent to the MTJ.

3. The method of claim 1, further comprising:

forming a pinned layer on the bottom electrode layer; and

forming a barrier layer on the pinned layer before forming the free layer.

4. The method of claim 1, wherein the bottom electrode layer comprises tantalum nitride (TaN).

5. The method of claim 4, wherein a concentration of nitrogen increases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.

6. The method of claim 4, wherein a concentration of tantalum decreases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.

7. The method of claim 4, wherein a ratio of nitrogen to tantalum at a top surface of the bottom electrode layer is between 1.53 to 1.87.

8. The method of claim 4, wherein a ratio of nitrogen to tantalum at a bottom surface of the bottom electrode layer is between 0.18 to 0.22.

9. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises;

a bottom electrode layer, wherein the bottom electrode layer comprises a gradient concentration;

a free layer on the bottom electrode layer; and

a top electrode layer on the free layer.

10. The semiconductor device of claim 9, further comprising:

a pinned layer on the bottom electrode layer; and

a barrier layer on the pinned layer.

11. The semiconductor device of claim 9, wherein the bottom electrode layer comprises tantalum nitride (TaN).

12. The semiconductor device of claim 11, wherein a concentration of nitrogen increases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.

13. The semiconductor device of claim 11, wherein a concentration of tantalum decreases from a bottom surface of the bottom electrode layer to a top surface of the bottom electrode layer.

14. The semiconductor device of claim 11, wherein a ratio of nitrogen to tantalum at a top surface of the bottom electrode layer is between 1.53 to 1.87.

15. The semiconductor device of claim 11, wherein a ratio of nitrogen to tantalum at a bottom surface of the bottom electrode layer is between 0.18 to 0.22.