METHODS TO IMPROVE MAGNETIC TUNNEL JUNCTION MEMORY CELLS

• US 20200136027A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Jung-Tang, Yu, Wu Meng, Wu, Szu-Hua, Lee, Chin-Szu
• Granted Patent: US 10,991,876 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a bottom electrode layer, wherein a dielectric layer overlies the bottom electrode layer;

performing a treatment to reduce the dielectric layer on the bottom electrode layer;

after performing the treatment, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;

forming a top electrode layer over the MTJ layer; and

patterning the top electrode layer, the MTJ layer, and the bottom electrode layer to form a magnetic random access memory (MRAM) cell.

2. The method of claim 1, wherein the treatment generates a gaseous by-product comprising steam.

3. The method of claim 1, further comprising forming the dielectric layer by exposing the bottom electrode layer to an oxygen-containing environment.

4. The method of claim 1, wherein the dielectric layer comprises TiO_xN_y or TiO₂.

5. The method of claim 1, wherein the treatment comprises exposing the dielectric layer to hydrogen radicals.

6. The method of claim 5, wherein the hydrogen radicals are produced in a remote plasma process.

7. The method of claim 1, wherein the treatment comprises a thermal treatment using H₂ as a reducing agent.

8. The method of claim 1, wherein the treatment comprises a thermal treatment using NH₃ as a reducing agent.

9. A method of forming a semiconductor structure, the method comprising:

forming a bottom electrode via in a dielectric stack, the dielectric stack comprising a first dielectric layer over a second dielectric layer;

forming a bottom electrode layer over the bottom electrode via and the dielectric stack;

reducing a dielectric layer on a surface of the bottom electrode layer, wherein reducing the dielectric layer produces a gaseous by-product;

after reducing the dielectric layer, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;

forming a top electrode layer over the MTJ layer; and

after forming the top electrode layer, patterning the top electrode layer, the MTJ layer, and the bottom electrode layer to form a magnetic random access memory (MRAM) cell.

10. The method of claim 9, wherein the dielectric layer is formed on the surface of the bottom electrode layer when the bottom electrode layer is exposed to an oxygen containing environment prior to the reducing the dielectric layer.

11. The method of claim 9, wherein the reducing comprises a generating H* using a plasma process using a carrier gas of Ar or N₂ at a flow rate of about 10 sccm to about 10000 sccm, a process gas of H₂ or NH₃ at a flow rate of about 10 sccm to about 10000 sccm, at a pressure of about 1 mTorr to about 10 Torr, a temperature of about 20°

C. to about 500°

C., a DC bias of about 0.1 kV to about 30 kV, and an RF power of about 100 W to about 2 kW at an excitation frequency of about 13 MHz to about 40 MHz.

12. The method of claim 9, wherein the dielectric layer comprises TiO₂ and wherein the reducing comprises exposing the dielectric layer to H* and generating a by-product of steam.

13. The method of claim 9, wherein the dielectric layer comprises TiO_xN_y and wherein the reducing comprises exposing the dielectric layer to H* and generating a by-product of steam.

14. The method of claim 9, wherein the dielectric layer comprises TiO₂ and wherein the reducing comprises using H₂ as a reducing agent at a pressure of about 1 mTorr to about 500 mTorr and a temperature of about 20°

C. to about 500°

C. for a time period of about 5 seconds to about 500 seconds.

15. The method of claim 9, wherein the dielectric layer comprises TiO_xN_y and wherein the reducing comprises using H₂ as a reducing agent at a pressure of about 1 mTorr to about 500 mTorr and a temperature of about 20°

C. to about 500°

C. for a time period of about 5 seconds to about 500 seconds.

16. The method of claim 9, wherein the dielectric layer comprises TiO₂ and wherein the reducing comprises using NH₃ as a reducing agent at a pressure of about 100 mTorr to about 500 mTorr and a temperature of about 20°

C. to about 500°

C. for a time period of about 10 seconds to about 1000 seconds.

17. The method of claim 9, wherein the dielectric layer comprises TiO_xN_y and wherein the reducing comprises using NH₃ as a reducing agent at a pressure of about 100 mTorr to about 500 mTorr and a temperature of about 20°

C. to about 500°

C. for a time period of about 10 seconds to about 1000 seconds.

18. A method of forming a semiconductor structure, the method comprising:

forming a bottom electrode via in a dielectric stack, the dielectric stack comprising a first dielectric layer over a second dielectric layer;

forming a bottom electrode layer over the bottom electrode via and the dielectric stack, the bottom electrode layer comprising a plurality of conductive layers;

reducing an oxide layer over the bottom electrode layer, wherein reducing the oxide layer exposes a conductive surface;

after reducing the oxide layer, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer, wherein the MTJ layer comprises a tunnel barrier layer interposed between a pinning layer and a free layer;

forming a top electrode layer over the MTJ layer; and

after forming the top electrode layer, patterning the top electrode layer, the MTJ layer, and the bottom electrode layer to form a magnetic random access memory (MRAM) cell, wherein patterning comprises recessing the dielectric stack.

19. The method of claim 18, wherein the oxide layer comprises a native oxide layer.

20. The method of claim 18, wherein recessing the dielectric stack comprises recessing the first dielectric layer.