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FULLY ALIGNED SEMICONDUCTOR DEVICE WITH A SKIP-LEVEL VIA

  • US 20200136028A1
  • Filed: 10/08/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/29/2018
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a memory element disposed on a first metal layer;

    a first cap layer disposed on the first metal layer and sidewalls of the memory element;

    a first dielectric layer disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element;

    a second metal layer disposed on the first dielectric layer and sidewalls of the first cap layer;

    a second cap layer disposed on a top surface of the second metal layer;

    a second dielectric layer disposed on the second cap layer;

    a via in the second dielectric layer and exposes a top surface of the memory element; and

    a third metal layer disposed on the second dielectric layer and in the via.

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