FULLY ALIGNED SEMICONDUCTOR DEVICE WITH A SKIP-LEVEL VIA
First Claim
1. A semiconductor structure comprising:
- a memory element disposed on a first metal layer;
a first cap layer disposed on the first metal layer and sidewalls of the memory element;
a first dielectric layer disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element;
a second metal layer disposed on the first dielectric layer and sidewalls of the first cap layer;
a second cap layer disposed on a top surface of the second metal layer;
a second dielectric layer disposed on the second cap layer;
a via in the second dielectric layer and exposes a top surface of the memory element; and
a third metal layer disposed on the second dielectric layer and in the via.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
-
Citations
20 Claims
-
1. A semiconductor structure comprising:
-
a memory element disposed on a first metal layer; a first cap layer disposed on the first metal layer and sidewalls of the memory element; a first dielectric layer disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element; a second metal layer disposed on the first dielectric layer and sidewalls of the first cap layer; a second cap layer disposed on a top surface of the second metal layer; a second dielectric layer disposed on the second cap layer; a via in the second dielectric layer and exposes a top surface of the memory element; and a third metal layer disposed on the second dielectric layer and in the via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 20)
-
-
11. An integrated circuit comprising:
-
one or more semiconductor structures, wherein one of the semiconductor structures comprises; a memory element disposed on a first metal layer; a first cap layer disposed on the first metal layer and sidewalls of the memory element; a first dielectric layer disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element; a second metal layer disposed on the first dielectric layer and sidewalls of the first cap layer; a second cap layer disposed on a top surface of the second metal layer; a second dielectric layer disposed on the second cap layer; a via in the second dielectric layer and exposes a top surface of the memory element; and a third metal layer disposed on the second dielectric layer and in the via. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
Specification