PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING

• US 20200136036A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, Jau-Yi, YU, Shao-Ming, TSAI, Shih-Chi
• Granted Patent: US 11,139,430 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A method includes forming a dielectric layer over a conductive layer, and forming a sidewall spacer in an opening in the dielectric layer. The opening exposes a portion of the conductive layer. A bottom electrode layer is formed over the conductive layer and the sidewall spacer. A phase change material layer is formed over the bottom electrode layer, and a top electrode layer is formed over the phase change material layer. In an embodiment, the method includes recess etching the bottom electrode layer before forming the phase change material layer.

Claims

1. A method, comprising:

forming a dielectric layer over a conductive layer;

forming a sidewall spacer in an opening in the dielectric layer,

wherein the opening exposes a portion of the conductive layer;

forming a bottom electrode layer over the conductive layer and the sidewall spacer;

forming a phase change material layer over the bottom electrode layer; and

forming a top electrode layer over the phase change material layer.

2. The method according to claim 1, further comprising recess etching the bottom electrode layer before forming the phase change material layer.

3. The method according to claim 1, further comprising forming a liner layer over the conductive layer and the sidewall spacer before forming the bottom electrode layer.

4. The method according to claim 1, further comprising planarizing the bottom electrode layer before forming the phase change material layer.

5. The method according to claim 1, wherein the forming the sidewall spacers comprises:

conformally depositing an insulating material layer over the conductive layer and the dielectric layer; and

anisotropically etching the insulating material layer to expose the conductive layer.

6. The method according to claim 1, further comprising planarizing the phase change material layer before forming the top electrode layer.

7. A method, comprising:

forming a first dielectric layer over a first conductive layer;

forming a first opening in the first dielectric layer exposing the first conductive layer;

filling the first opening with a second dielectric layer;

forming a second opening in the second dielectric layer exposing the first conductive layer,

wherein a width of second opening is less than a width of the first opening;

forming a second conductive layer in the second opening;

forming a phase change material layer over the second conductive layer;

forming a selector layer over the phase change material layer; and

forming a third conductive layer over the selector layer.

8. The method according to claim 7, further comprising recess etching the second conductive layer before forming the phase change material layer.

9. The method according to claim 7, further comprising forming a liner layer over the first conductive layer and the second dielectric layer before forming the second conductive layer.

10. The method according to claim 7, further comprising planarizing the second conductive layer before forming the phase change material layer.

11. The method according to claim 7, wherein the forming a second opening in the second dielectric layer comprises anisotropically etching the second dielectric layer to expose the first conductive layer.

12. The method according to claim 7, wherein the forming a first opening in the first dielectric layer exposing the first conductive layer comprises:

forming a photoresist layer over the first dielectric layer;

patterning the photoresist layer to form an opening in the photoresist layer to expose a portion of the first dielectric layer; and

etching the first dielectric layer through the opening in the photoresist layer to expose the first conductive layer.

13. The method according to claim 7, further comprising forming a fourth conductive layer over the phase change material layer before forming selector layer.

14. A phase change random access memory device, comprising:

a dielectric layer with a trench formed therein disposed over a conductive layer;

a sidewall spacer disposed on a sidewall of the dielectric layer in the trench;

a bottom electrode layer disposed over the conductive layer and the sidewall spacer;

a phase change material layer disposed over the bottom electrode; and

a top electrode layer disposed over the phase change material layer.

15. The phase change random access memory device of claim 14, wherein the bottom electrode layer is substantially trapezoidal shaped in cross section.

16. The phase change random access memory device of claim 14, wherein the phase change material is formed over the sidewall spacer.

17. The phase change random access memory device of claim 14, wherein an upper surface of the phase change material layer is flush with an upper surface of the sidewall spacer.

18. The phase change random access memory device of claim 14, further comprising a liner layer disposed between the bottom electrode layer, and conductive layer and the sidewall spacer.

19. The phase change random access memory device of claim 14, wherein the top electrode layer is in direct contact with an upper surface of the sidewall spacer.

20. The phase change random access memory device of claim 14, wherein the phase change material comprises one or more layers of a binary system of Ga—

Sb, In—

Sb, In—

Se, Sb—

Te, Ge—

Te, and Ge—

Sb;

a ternary system, of Ge—

Sb—

Te, In—

Sb—

Te, Ga—

Se—

Te, Sn—

Sb—

Te, In—

Sb—

Ge, and Ga—

Sb—

Te;

a quaternary system of Ag—

In—

Sb—

Te, Ge—

Sn—

Sb—

Te, Ge—

Sb—

Se—

Te, Te—

Ge—

Sb—

S, Ge—

Sb—

Te—

O, and Ge—

Sb—

Te—

N;

a chalcogenide alloy containing one or more elements from Group VI of the periodic table, a Ge—

Sb—

Te alloy, Ge₂Sb₂Te₅, tungsten oxide, nickel oxide, copper oxide, or combinations thereof.