INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES

• US 20200136038A1
• Filed: 05/15/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Manfrini, Mauricio, Lin, Chung-Te, Doornbos, Gerben, van Dal, Marcus Johannes Henricus
• Granted Patent: US 10,971,684 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric lower, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

Claims

1. An integrated chip including a memory device, the memory device comprising:

a bottom electrode disposed over a semiconductor substrate;

an upper electrode disposed over the bottom electrode; and

an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

2. The integrated chip of claim 1, wherein when the memory device is in a first state, a lower conductive filament extends from the bottom electrode through the lower dielectric layer and to the first metal layer, and an upper conductive filament extends from the first metal layer through the upper dielectric layer and to the upper electrode.

3. The integrated chip of claim 2, wherein when the memory device is in a second state, at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer separates the bottom electrode from the first metal layer, and/or at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer separates the first metal layer from the upper electrode.

4. The integrated chip of claim 1, wherein the intercalated metal/dielectric structure further comprises:

a second metal layer disposed over the upper dielectric layer, the second metal layer separating the upper dielectric layer from the upper electrode.

5. The integrated chip of claim 1, wherein the intercalated metal/dielectric structure further comprises:

a second metal layer disposed over the bottom electrode, the second metal layer separating the bottom electrode from the lower dielectric layer.

6. The integrated chip of claim 5, wherein the intercalated metal/dielectric structure further comprises:

a third metal layer disposed over the upper dielectric layer, the third metal layer separating the upper dielectric layer from the upper electrode.

7. The integrated chip of claim 6, wherein the upper dielectric layer and lower dielectric layer comprise a high-k dielectric material;

the first metal layer, the second metal layer, and the third metal layer comprise copper, aluminum, or tungsten; and

the upper electrode and the bottom electrode comprise tantalum or titanium.

8. The integrated chip of claim 1, further comprising a resistive random access memory (RRAM) cell disposed over the upper electrode, the RRAM cell comprising:

a data storage dielectric layer disposed over the upper electrode; and

a top electrode disposed over the data storage dielectric layer.

9. The integrated chip of claim 1, further comprising:

a dielectric liner along sidewalls of the intercalated metal/dielectric structure.

10. An integrated chip, comprising:

an interconnect structure including a lower metal layer and an upper metal layer which are separated from one another by a first inter-level dielectric (ILD) layer;

a bottom electrode disposed over the lower metal layer;

a top electrode disposed over the bottom electrode, the top electrode residing below the upper metal layer; and

a plurality of metal layers and a plurality of dielectric layers stacked in alternating fashion over one another and sandwiched between the top electrode and the bottom electrode.

11. The integrated chip of claim 10, wherein at least two of the plurality of metal layers have different thicknesses from one another.

12. The integrated chip of claim 10, wherein at least two of the plurality of dielectric layers have different thicknesses from one another.

13. The integrated chip of claim 10, wherein a maximum thickness of any of the plurality of dielectric layers is less than 10 nm.

14. The integrated chip of claim 10, wherein the plurality of dielectric layers include a plurality of conductive filaments, respectively, wherein each conductive filament extends through a corresponding dielectric layer to couple neighboring metal layers in the plurality of metal layers to one another.

15. A method, comprising:

forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over a substrate;

forming an intercalated metal/dielectric structure over the lower interconnect structure, the intercalated metal/dielectric structure comprising a lower dielectric layer over the lower interconnect structure, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer; and

forming an upper electrode over the intercalated metal/dielectric structure.

16. The method of claim 15, further comprising:

forming a memory element over the upper electrode;

forming a top electrode over the memory element; and

patterning the top electrode, the memory element, the upper electrode, and the intercalated metal/dielectric structure, thereby forming a patterned device structure.

17. The method of claim 16, further comprising:

forming a second ILD layer over the patterned device structure; and

forming a via and top metal line within the second ILD layer, wherein the via couples the top metal line to an upper portion of the upper electrode.

18. The method of claim 15, wherein the intercalated metal/dielectric structure includes five or fewer dielectric layers between the lower interconnect structure and the upper electrode.

19. The method of claim 15, further comprising:

applying a first bias between the lower interconnect structure and the upper electrode to induce a first state in the intercalated metal/dielectric structure;

wherein in the first state, a lower conductive filament extends from the lower interconnect structure through the lower dielectric layer and to the first metal layer, and an upper conductive filament extends from the first metal layer through the upper dielectric layer and to the upper electrode.

20. The method of claim 19, further comprising:

applying a second bias between the lower interconnect structure and the upper electrode to induce a second state in the intercalated metal/dielectric structure;

wherein in the second state, at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer separates the lower interconnect structure from the first metal layer, and/or at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer separates the first metal layer from the upper electrode.