PAD PROTECTION IN AN INTEGRATED CIRCUIT

• US 20200136373A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: ABHISHEK, KUMAR, Jagannathan, Srikanth
• Granted Patent: US 11,146,057 B2
• Time in Patent Office: Days
• CPC Class Codes: H02H 7/205 for controlled semi-conductors which are not included in a specific circuit arrangement
• CPC Class Codes: H03K 19/018592 with a bidirectional operation

Abstract

An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.

Claims

1. In an integrated circuit (IC) having a signal pad configured to communicate external to the IC, an output buffer coupled to provide signals to the signal pad and an input buffer coupled to receive signals from the signal pad, a method comprising:

determining that a voltage on the signal pad is both greater than a predetermined low threshold voltage and lower than a predetermined high threshold voltage for a continuous amount of time greater than a predetermined period of time, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one; and

in response to determining that the voltage on the signal pad is both greater than the predetermined low threshold voltage and lower than the predetermined high threshold voltage for the continuous amount of time greater than the predetermined period of time, disabling the input buffer such that no signal from the signal pad is transmitted through the input buffer.

2. The method of claim 1, in response to determining that the voltage on the signal pad is both greater than the predetermined low threshold voltage and lower than the predetermined high threshold voltage for the continuous amount of time greater than the predetermined period of time, disabling both the input and output buffers.

3. The method of claim 2, wherein, in response to determining that the voltage on the signal pad is both greater than the predetermined low threshold voltage and lower than the predetermined high threshold voltage for the continuous amount of time greater than the predetermined period of time, latching a value which disables both the input and output buffers.

4. The method of claim 3, wherein the value which disables both the input and output buffers remains latched and continues to disable both the input and output buffers even if the voltage on the signal pad goes higher than the predetermined high threshold voltage or lower than the predetermined low threshold voltage.

5. The method of claim 4, further comprising:

providing a reset signal to reset the latch such that the latch no longer disables the input and output buffers.

6. The method of claim 5, wherein the latch is further characterized as a D flip lop.

7. The method of claim 1, further comprising:

after disabling the input buffer, when the voltage on the signal pad either goes higher than the predetermined high threshold voltage or goes lower than the predetermined low threshold voltage, reenabling the input buffer.

8. The method of claim 7, wherein a switch point of the input buffer is at a voltage between the high predetermined threshold voltage and low predetermined threshold voltage, and wherein the input buffer is disabled at least while the voltage on the signal pad is crossing the switch voltage.

9. A integrated circuit comprising:

a signal pad;

an output buffer having an output coupled to the signal pad and having an enable input;

an input buffer having an input coupled to the signal pad and having an enable input;

a counter which is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one; and

a gating circuit, coupled to the counter and the enable inputs of the input and output buffers, configured to, in response to the counter expiring, disable the input buffer and the output buffer.

10. The integrated circuit of claim 9, further comprising:

a first comparator having a first input coupled to receive the predetermined high threshold voltage and a second input coupled to the signal pad; and

a second comparator having a first input coupled to receive the predetermined low threshold voltage and a second input coupled to the signal pad, wherein when both the first comparator indicates that the voltage on the signal pad is lower than the predetermined high threshold voltage and the second comparator indicators that the voltage on the signal pad is higher than the predetermined low threshold voltage, the counter is enabled.

11. The integrated circuit of claim 10, wherein the gating circuit further comprises:

a latch having a clock input and an output, wherein the latch is configured to latch a gating value when the counter expires, wherein the gating value forces the input buffer and the output buffer to be disabled.

12. The integrated circuit of claim 11, wherein the latch comprises a D flip flop having a clock input coupled to a counter expired indicator from the counter, a data input coupled to receive the gating value, and an output coupled to provide a gating indicator to control the enable inputs of the input buffer and the output buffer.

13. The integrated circuit of claim 11, wherein the latch includes a reset input, wherein the latch is configured to, when the reset input is asserted, reset the gating value such that it no longer forces the input buffer and the output buffer to be disabled.

14. The integrated circuit of claim 9, further comprising:

a first comparator having a non-inverting input coupled to receive the predetermined high threshold voltage and an inverting input coupled to the signal pad; and

a second comparator having an inverting input coupled to receive the predetermined low threshold voltage and a non-inverting input coupled to the signal pad.

15. The integrated circuit of claim 14, further comprising:

an AND gate having a first input coupled to an output of the first comparator, a second input coupled to an output of the second comparator, and an output coupled to provide a counter enable signal to an enable input of the counter.

16. The integrated circuit of claim 15, wherein the gating circuit further comprising:

a D flip flop having a data input coupled to ground, a data output coupled to provide a gating output to control disabling of the input and output buffers, a clock input coupled to receive a counter expired signal from the counter, and a reset input coupled to receive a reset signal;

a first AND gate having a first input coupled to receive an input output buffer enable (OBE) signal, a second input coupled to receive the gating output, and an output coupled to an enable input of the output buffer; and

a second AND gate having a first input coupled to receive an input input buffer enable (IBE) signal, a second input coupled to receive the gating output, and an output coupled to an enable input of the input buffer.

17. The integrated circuit of claim 9, wherein the signal pad, output buffer, and input buffer are included in a first pad circuit, the integrated circuit further comprising:

a first switch coupled between the signal pad of the first pad circuit and the counter;

second pad circuit having a second signal pad, a second output buffer coupled to the second signal pad, and a second input buffer coupled to the second signal pad, wherein the gating circuit is also coupled to the second output buffer and second input buffer;

a second switch coupled between the second signal pad of the second pad circuit and the counter, wherein;

when the first switch is closed and the second switch is open;

the counter is enabled to start counting down the predetermined count value when the voltage on the signal pad is both higher than the predetermined low threshold voltage and lower than the predetermined high threshold voltage, and the gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer; and

when the first switch is open and the second switch is closed;

the counter is enabled to start counting down the predetermined count value when a voltage on the second signal pad is both higher than the predetermined low threshold voltage and lower than the predetermined high threshold voltage, and the gating circuit is configured to, in response to the counter expiring, disable the second input buffer and the second output buffer.

18. A integrated circuit comprising:

a reset signal pad coupled to receive a reset signal from an external source;

an output buffer having an output coupled to the reset signal pad;

an input buffer having an enable input coupled to receive an enable signal and a data input coupled to the reset signal pad;

a counter having;

a counter enable input wherein the counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one, and

a counter expired output configured to provide a gating value, wherein when the counter expires, the gating value forces the enable input to disable the input buffer until the counter is reset and while the counter is not expired, the gating value allows the input buffer to be selectively enabled and disabled.

19. The integrated circuit of claim 18, further comprising:

a first comparator having a first input coupled to receive the predetermined high threshold voltage and a second input coupled to the signal pad; and

a second comparator having a first input coupled to receive the predetermined low threshold voltage and a second input coupled to the signal pad, wherein when both the first comparator indicates that the voltage on the signal pad is lower than the predetermined high threshold voltage and the second comparator indicators that the voltage on the signal pad is higher than the predetermined low threshold voltage, the counter is enabled.

20. The integrated circuit of claim 19, wherein a switch voltage of the input buffer is at a voltage between the high predetermined threshold voltage and low predetermined threshold voltage, wherein when the counter expires, the gating value forces the enable input to disable the buffer while the voltage on the signal pad is crossing the switch voltage.