DRIVE CIRCUIT AND METHOD FOR CORRECTING INTERNAL OVERCURRENT SETTING VALUE THEREOF

• US 20200136377A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 08/31/2018
• Status: Active Grant

• Current Assignee: Chongqing HKC Optoelectronics Technology Co., Ltd. (Shenzhen Huike Investment Holding Co., Ltd.), HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Original Assignee: HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Inventors: Wang, Mingliang
• Granted Patent: US 11,038,343 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1333 Constructional arrangements; Manufacturing methodsG02F1/135, G02F1/136 take precedence
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/025 Reduction of instantaneous peaks of current
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: H02H 9/02 responsive to excess current current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025

Abstract

Embodiments of the present disclosure provide a drive circuit and a method for correcting internal overcurrent setting value thereof. The first current signal output from the first chip is converted into the second current signal which is configured to adjust the internal overcurrent setting value of the second chip by the timing controller.

Claims

1. A drive circuit comprising a first chip and a second chip, wherein the drive circuit further comprises:

a current detector configured to obtain a first current signal output from the first chip; and

a timing controller, configured to receive the first current signal and convert the first current signal into a second current signal which is configured to adjust an internal overcurrent setting value of the second chip.

2. The drive circuit of claim 1, wherein the second chip comprises:

a booster configured to boost an input first logic signal and output a second logic signal; and

an overcurrent setting circuit configured to perform current-limiting control on the second logic signal according to the internal overcurrent setting value.

3. The drive circuit of claim 2, wherein the second chip is a boost chip.

4. The drive circuit of claim 1, wherein the first chip is a power management chip.

5. The drive circuit of claim 1, wherein the current detector comprises:

a first converter configured to convert the first current signal output from the first chip into a corresponding first data signal; and

a first storage configured to store the first data signal.

6. The drive circuit of claim 5, wherein the timing controller comprises:

a second storage configured to set and store a second data signal corresponding to the first data signal; and

a controller configured to obtain the first data signal and obtain the second data signal from the second storage according to the first data signal.

7. The drive circuit of claim 2, wherein:

the current detector comprises a first converter configured to convert the first current signal output from the first chip into a corresponding first data signal and a first storage configured to store the first data signal;

the timing controller comprises a second storage configured to set and store a second data signal corresponding to the first data signal and a controller configured to obtain the first data signal and obtain the second data signal from the second storage according to the first data signal;

the overcurrent setting circuit is further configured to receive the second data signal and setting the second data signal to the internal overcurrent setting value.

8. The drive circuit of claim 2, wherein the overcurrent setting circuit is further configured to set the current value of the second current signal to the internal overcurrent setting value.

9. The drive circuit of claim 2, wherein the overcurrent setting circuit is further configured to turn off the output of the second logic signal when the second logic signal is greater than or equal to the internal overcurrent setting value.

10. The drive circuit of claim 1, wherein the timing controller is connected to the current detector via an I2C interface.

11. A drive circuit, comprising:

a power management chip configured to output a first current signal;

a boost chip configured to boost an input first logic signal to output a second logic signal, and perform current-limiting control on the second logic signal according to an internal overcurrent setting value;

a current detector configured to obtain the first current signal; and

a timing controller, configured to receive the first current signal and convert the first current signal into a second current signal which is configured to adjust the internal overcurrent setting value of the boost chip.

12. The drive circuit of claim 11, wherein the current detector comprises:

a first converter configured to convert the first current signal into a corresponding first data signal; and

a first storage configured to store the first data signal.

13. The drive circuit of claim 12, wherein the timing controller comprises:

a second storage configured to set and store a second data signal corresponding to the first data signal; and

a controller configured to obtain the first data signal and obtain the second data signal from the second storage according to the first data signal.

14. The drive circuit of claim 13, wherein the second data signal is configured to correct the internal overcurrent setting value.

15. A method for correcting internal overcurrent setting value of a drive circuit, wherein the drive circuit comprises:

a first chip configured to output a first current signal; and

a second chip configured to receive a first logic signal, and boost the first logic signal to output a second logic signal;

the method comprising;

obtaining the first current signal output from the first chip;

receiving the first current signal and converting the first current signal into a second current signal, wherein the second current signal is configured to adjust an internal overcurrent setting value of the second chip and the internal overcurrent setting value is configured to perform current-limiting control on the second logic signal.

16. The method of claim 15, wherein obtaining the first current signal output from the first chip comprises:

using a current detector to obtain the first current signal output from the first chip.

17. The method of claim 15, wherein receiving the first current signal and converting the first current signal into a second current signal comprises:

receiving the first current signal; and

converting the first current signal into the second current signal according to the first current signal and a preset current conversion relationship table.

18. The method of claim 17, wherein converting the first current signal into the second current signal according to the first current signal and a preset current conversion relationship table comprises:

obtaining a first current value of the first current signal;

obtaining a second current value from the preset current conversion relationship table according to the first current value; and

converting the first current signal to the second current signal according to the second current value.

19. The method of claim 15, wherein the second current signal is configured to adjust an internal overcurrent setting value of the second chip by:

setting the current value of the second current signal to the internal overcurrent setting value.

20. The method of claim 15, wherein the internal overcurrent setting value is configured to perform current-limiting control on the second logic signal by:

stopping output of the second logic signal in the case that a current value of the second logic signal is equal to or greater than the internal overcurrent setting value.