VOLTAGE LIMITING DEVICE

• US 20200136380A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Mathew, Anu, Quax, Guido Wouter Willem
• Granted Patent: US 10,938,203 B2
• Time in Patent Office: Days
• CPC Class Codes: H02H 9/044 Physical layout, materials not provided for elsewhere varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.

Claims

1. A voltage limiting device, comprising:

a first I/O port;

a second I/O port;

a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit;

wherein the voltage limiter includes a first portion and a second portion;

wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and

wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.

2. The device of claim 1:

wherein if the voltage received is a negative voltage with reference to the ground, then the voltage limiter is configured to shunt the negative voltage received if less than a negative voltage limit.

3. The device of claim 2:

further comprising, another voltage limiter, coupled to the first and second I/O ports, and configured to shunt a positive voltage greater than a positive voltage limit received on the first and/or second I/O ports.

4. The device of claim 1:

wherein the voltage received is a positive voltage with reference to the ground; and

wherein the voltage limiter is configured to shunt the positive voltage received if greater than a positive voltage limit.

5. The device of claim 4:

further comprising, another voltage limiter, coupled to the first and second I/O ports, and configured to shunt a negative voltage less than a negative voltage limit received on the first and/or second I/O ports.

6. The device of claim 1:

wherein the current shunts are diodes.

7. The device of claim 1:

wherein the current shunts are gate-grounded NMOS devices.

8. The device of claim 1:

wherein the current shunts are PNP ESD clamps.

9. The device of claim 1:

wherein the voltage limiting device is an electrostatic discharge (ESD) limiting device.

10. The device of claim 1:

wherein a minimum current carrying size of the current shunts is based on a minimum electrostatic discharge (ESD) protection level of the voltage limiting device.

11. The device of claim 1:

wherein the voltage limiter includes an equivalent capacitance based on a ratio of capacitances of the first portion of the voltage limiter to the second portion of the voltage limiter; and

wherein the ratio of capacitance is a monotonically increasing function with an increasing capacitance of the first portion.

12. The device of claim 1:

wherein a capacitance of the current shunt in the second portion of the voltage limiter is greater than capacitances of the current shunts in the first portion of the voltage limiter.

13. The device of claim 1:

wherein capacitances of the current shunts in the first portion of the voltage limiter are same; and

wherein a capacitance of the current shunt in the second portion of the voltage limiter is twice the capacitances of the current shunts in the first portion of the voltage limiter.

14. The device of claim 1:

wherein the first and/or second I/O port are configured to be embedded in a USB communications cable.

15. The device of claim 1:

wherein the first and/or second I/O port are configured to be coupled to a set of electronics to be protected from an electrostatic discharge (ESD) strike.

16. The device of claim 1:

wherein the first and second I/O ports are configured to carry bi-directional signals.

17. The device of claim 1:

further comprising a negative voltage charge pump is coupled to the mid-net and configured to bias the mid-net with a negative voltage which reduces the capacitance of the voltage limiter.

18. The device of claim 4:

further comprising a positive voltage charge pump coupled to the voltage limiter and configured to bias the voltage limiter with a positive voltage which reduces the capacitance of the voltage limiter.

19. The device of claim 1:

further comprising a signaling switch configured to enable and disable communication signals between the first and second I/O ports.

20. The device of claim 19:

wherein at least one of the current shunts is a diode formed from an isolated P-well in the switch.

21. The device of claim 19:

wherein the signaling switch is a MOSFET and a gate of the MOSFET is configured to be opened when the received voltage is greater than the absolute value of the voltage limit; and

wherein the open gate is configured to create an additional current shunt for reducing the absolute value of the received voltage.

22. The device of claim 19:

further comprising a floating body resistance coupled between the signaling switch and the ground.