DC-DC CONVERTER HAVING A SWITCH ON-TIME CONTROL LOOP WITH A SWITCHED-CAPACITOR CIRCUIT FOR ERROR-BASED ADJUSTMENT

• US 20200136494A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: KAZAMA, Taisuke, YOSHIOKA, Masahiro
• Granted Patent: US 10,770,963 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

An apparatus includes a direct-current to direct-current (DC-DC) converter having an output node and at least one electronic switch. The DC-DC converter also includes: 1) a first feedback loop configured to control a voltage at the output node by adjusting a first switching parameter of the at least one electronic switch; and 2) a second feedback loop configured to adjust a second switching parameter of the at least one electronic switch. The second feedback loop includes a switched-capacitor circuit configured to determine a threshold signal based on an error between a reference signal and a control signal for the at least one electronic switch. The second feedback loop is configured to adjust the second switching parameter based on a comparison of an on-time signal with the threshold signal.

Claims

1. A system that comprises:

a direct-current to direct-current (DC-DC) converter having;

an output node;

at least one electronic switch;

a first feedback loop configured to control a voltage at the output node by adjusting a first switching parameter of the at least one electronic switch; and

a second feedback loop configured to adjust a second switching parameter of the at least one electronic switch, wherein the second feedback loop includes a switched-capacitor circuit configured to provide a threshold signal based on an error between a reference signal and a control signal for the at least one electronic switch, and wherein the second feedback loop is configured to adjust the second switching parameter based on a comparison of an on-time signal with the threshold signal.

2. The system of claim 1, wherein first switching parameter is a duty cycle and the second switching parameter is a switching frequency.

3. The system of claim 1, wherein the switched-capacitor circuit comprises a differential integrator and a summer circuit configured to adjust the threshold signal based on the error.

4. The system of claim 3, further comprising an RC filter at the output of the differential integrator and configured to eliminate noise generated at the differential integrator, wherein the output of the RC filter corresponds to the threshold signal.

5. The system of claim 1, wherein the second feedback loop is configured to adjust the threshold signal such that an average switching frequency applied to the at least one electronic switch equals a target switching frequency.

6. The system of claim 1, further comprising a reference clock and a clock divider for the reference clock, wherein an output of the clock divider is the reference signal, and wherein the control signal is configured to lock to the reference signal.

7. The system of claim 1, further comprising a clock divider configured to receive the control signal and to provide a lower frequency version of the control signal, wherein the second feedback loop is configured to lock the control signal to a frequency that is multiple times higher than the reference signal.

8. The system of claim 1, wherein the switched-capacitor circuit includes first and second branches configured to determine the error between the reference signal and the control signal, wherein the control signal is a pulse width modulation (PWM) signal.

9. The system of claim 8, wherein the first branch comprises a first capacitor between a first switch and a second switch configured to convert the reference signal into a first current level, wherein the second branch comprises a second capacitor between a third switch and a fourth switch configured to convert the control signal into a second current level, and wherein the difference between the first and second current levels is used as the error.

10. The system of claim 8, wherein the first and second branches are configured to generate a positive current as the error when the reference signal has a higher frequency than the PWM signal, and to generate a negative current as the error when the reference signal has a lower frequency than the PWM signal, and wherein first and second branches are configured to provide the error to a differential integrator comprising an operational amplifier with a feedback loop having a third capacitor configured to integrate the error over time.

11. The system of claim 1, wherein the second feedback loop is configured to support automatic tuning of an integration time constant for compatibility with different reference signal frequencies.

20. The DC-DC converter device of claim 1, wherein the second feedback loop is configured to support automatic tuning of an integration time constant for compatibility with different reference signal frequencies.

12. A direct-current to direct-current (DC-DC) converter device that comprises:

an output node;

at least one electronic switch;

a first feedback loop with a first comparator configured to provide a first comparator output based on a comparison of the voltage at the output node and a reference voltage, wherein the first feedback loop is configured to adjust a first switching parameter of the at least one electronic switch based on the first comparator output; and

a second feedback loop with a second comparator and a switched-capacitor circuit, wherein the switched-capacitor circuit is configured to provide a threshold signal based on an error between a reference signal and a pulse width modulation (PWM) signal, wherein the second comparator is configured to provide a second comparator output based on a comparison of an on-time signal related to the at least one switch and the threshold signal, and wherein the second feedback loop is configured to adjust a second switching parameter of the at least one electronic switch based on the second comparator output.

13. The DC-DC converter device of claim 12, wherein first switching parameter is a duty cycle and the second switching parameter is a switching frequency.

14. The DC-DC converter device of claim 12, wherein the switched-capacitor circuit comprises a differential integrator and a summer circuit configured to adjust the threshold signal based on the error.

15. The DC-DC converter device of claim 14, further comprising an RC filter at the output of the differential integrator and configured to eliminate noise generated at the differential integrator, wherein the output of the RC filter corresponds to the threshold signal.

16. The DC-DC converter device of claim 12, further comprising a reference clock and a clock divider for the reference clock, wherein an output of the clock divider is the reference signal, and wherein PWM logic is configured to lock the PWM signal to the reference signal.

17. The DC-DC converter device of claim 12, further comprising a clock divider configured to receive the PWM signal and to provide a lower frequency version of the PWM signal, wherein the second feedback loop is configured to lock the PWM signal to a frequency that is multiple times higher than the reference signal.

18. The DC-DC converter device of claim 12, wherein the switched-capacitor circuit includes first and second branches configured to determine the error between the reference signal and the PWM signal, wherein the first branch comprises a first capacitor between a first switch and a second switch configured to convert the reference signal into a first current level, wherein the second branch comprises a second capacitor between a third switch and a fourth switch configured to convert the PWM signal into a second current level, and wherein the difference between the first and second current levels is used as the error.

19. The DC-DC converter device of claim 18, wherein the first and second branches are configured to generate a positive current as the error when the reference signal has a higher frequency than the PWM signal, and to generate a negative current as the error when the reference signal has a lower frequency than the PWM signal, and wherein the st and second branches are configured to provide the error to a differential integrator comprising an operational amplifier with a feedback loop having a third capacitor configured to integrate the error over time.

21. A direct-current to direct-current (DC-DC) converter circuit that comprises:

an output node between a first switch and a second switch;

an output inductor having a first side and a second side, wherein the first side of the output inductor couples to the output node;

an output capacitor having a first side and a second side, wherein the first side of the output capacitor couples to the second side of the output inductor, and wherein the second side of the output capacitor couples to a ground node;

driver circuitry coupled to the first and second switches;

pulse width modulation (PWM) logic coupled to the driver circuitry;

a frequency-locked loop (FLL) with a switched-capacitor circuit, wherein a first input node of the FLL couples to the first side of the output capacitor, a second input node of the FLL couples to a reference clock node, a third input node of the FLL couples to an output node of the PWM logic; and

a comparator with an input node coupled to an output node of the FLL, with a reference node coupled to an on-time signal circuit, and with an output node coupled to an input node of the PWM logic.

22. The DC-DC converter circuit of claim 21, wherein the switched-capacitor circuit includes first and second branches,

wherein the first branch comprises a first capacitor having a first side and a second, wherein the first side of the first capacitor is coupled to a voltage source node via a first switch and is coupled to a ground node via a second switch, wherein the second side of the first capacitor is coupled to a ground node via a third switch and is coupled to an input node of an integrator circuit via a fourth switch, wherein the second and third switches are coupled to a first control signal node, and wherein the first and fourth switches are coupled to a second control signal node,

wherein the second branch comprises a second capacitor having a first side and a second, wherein the first side of the second capacitor is coupled to a ground node via a fifth switch and is coupled to a ground node via a sixth switch, wherein the second side of the second capacitor is coupled to a ground node via a seventh switch and is coupled to the input node of an integrator circuit via an eighth switch, wherein the sixth and eighth switches are coupled to a third control signal node, and wherein the fifth and seventh switches are coupled to a fourth control signal node.