MULTI-STAGE CHARGE PUMP REGULATION ARCHITECTURE

• US 20200136502A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: LIU, Xiaoqun, VEMULA, Madan Mohan Reddy
• Granted Patent: US 10,826,386 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state

Abstract

A multi-stage charge pump including a first stage configured to generate a first output voltage, a last stage configured to receive the first output voltage from the first stage and output a second output voltage, a switch configured to receive the second output voltage from the last stage, and a voltage regulator circuit configured to control the second output voltage of the last stage to maintain a substantially constant on-resistance of the switch.

Claims

1. A multi-stage charge pump, comprising:

a first stage configured to generate a first output voltage;

a last stage configured to receive the first output voltage from the first stage and output a second output voltage;

a switch configured to receive the second output voltage from the last stage; and

a voltage regulator circuit configured to control the second output voltage of the last stage to maintain a substantially constant on-resistance of the switch.

2. The multi-stage charge pump according to claim 1, wherein the multi-stage charge pump voltage regulator circuit includes a comparator configured to compare the difference between the second output voltage and a reference voltage to an output voltage of the switch.

3. The multi-stage charge pump according to claim 2, wherein the comparator includes first and second NMOS transistors, and first and second PMOS transistors.

4. The multi-stage charge pump according to claim 2, wherein the comparator includes a cascode configuration of transistors configured to add at least one of additional accuracy and less variation to the multi-stage charge pump.

5. The multi-stage charge pump according to claim 2, wherein the comparator includes a plurality of extended drain transistors configured to withstand a high output voltage from the last stage.

6. The multi-stage charge pump according to claim 2, wherein the comparator outputs a high signal to enable the last stage of the multi-stage charge pump when the comparator determines that the difference between the second output voltage and the reference voltage is less than the output voltage of the switch.

7. The multi-stage charge pump according to claim 2, wherein the comparator outputs a low signal to disable the last stage of the multi-stage charge pump when the comparator determines that the difference between the second output voltage and the reference voltage is greater than the output voltage of the switch.

8. The multi-stage charge pump according to claim 1, comprising an AND gate configured to receive an output from the voltage regulator and a clock signal.

9. A method of regulating an output voltage of a multi-stage charge pump, comprising:

generating a first output voltage using a first stage of the multi-stage charge pump;

generating a second output voltage using a last stage of the multi-stage charge pump;

outputting the second output voltage to a switch; and

comparing the difference between the second output voltage and a reference voltage to an output voltage of the switch to determine whether a last stage of the multi-stage output is enabled.

10. The method of claim 9, wherein when the difference between the compared output voltage of the multi-stage charge pump and the reference voltage is less than the output voltage of the switch, a high signal is produced to enable the last stage of the multi-stage charge pump.

11. The method of claim 9, wherein when the difference between the compared output voltage of the multi-stage charge pump and the reference voltage is greater than the output voltage of the switch, a low signal is produced to disable the last stage of the multi-stage charge pump.

12. The method of claim 9, comprising generating an alternating on and off signal from a voltage regulator to alternately enable and disable the last stage and produce a substantially constant gate-source voltage of the switch over time.

13. The method of claim 12, comprising receiving the alternating on and off signal into an AND gate to alternately enable and disable the last stage.

14. A method of operating a multi-stage charge pump, comprising:

generating a first output voltage using a first stage;

receiving the first output voltage from the first stage and outputting a second output voltage by a last stage;

receiving the second output voltage from the last stage to control a switch; and

controlling the second output voltage of the last stage using a voltage regulator to maintain a substantially constant on-resistance of the switch.

15. The method of claim 14, comprising comparing the difference between the second output voltage and a reference voltage to an output voltage of the switch using a comparator.

16. The method of claim 15, wherein the comparator includes first and second NMOS transistors, and first and second PMOS transistors.

17. The method of claim 15, wherein the comparator includes a cascode configuration of transistors configured to add at least one of additional accuracy and less variation to the multi-stage charge pump.

18. The method of claim 15, comprising outputting a high signal to enable the last stage of the multi-stage charge pump when a comparator determines that the difference between the second output voltage and the reference voltage is less than the output voltage of the switch.

19. The method of claim 15, comprising outputting a low signal to disable the last stage of the multi-stage charge pump when it is determined that the difference between the second output voltage and the reference voltage is greater than the output voltage of the switch.

20. The method of claim 14, comprising receiving an output from the voltage regulator and a clock signal into a logic gate.