MULTI-STAGE CHARGE PUMP WITH INTER-STAGE LIMITATION CIRCUIT

• US 20200136503A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: LIU, Xiaoqun, VEMULA, Madan Mohan Reddy
• Granted Patent: US 10,811,963 B2
• Time in Patent Office: Days
• CPC Class Codes: H02H 9/025 Current limitation using field effect transistors
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Abstract

A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.

Claims

1. A multi-stage charge pump circuit, comprising:

a first stage of the multi-stage charge pump having a first voltage output;

a last stage of the multi-stage charge pump having a first voltage input; and

an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.

2. The multi-stage charge pump circuit of claim 1, wherein the first voltage output of the first stage of the multi-stage charge pump connects to the first voltage input of the last stage of the multi-stage charge pump through the inter-stage limitation circuit.

3. The multi-stage charge pump circuit of claim 1, wherein the inter-stage limitation circuit includes a PMOS transistor in parallel with a large size resistor.

4. The multi-stage charge pump circuit of claim 3, wherein the PMOS transistor is configured to be ON during a steady state action of the multi-stage charge pump.

5. The multi-stage charge pump circuit of claim 3, wherein the PMOS transistor is configured to be OFF when the first voltage input drops from a high state to a low state.

6. The multi-stage charge pump circuit of claim 1, wherein the inter-stage limitation circuit includes a first storage capacitor associated with the first voltage output.

7. The multi-stage charge pump circuit of claim 1, wherein the inter-stage limitation circuit includes a second storage capacitor associated with the first voltage input.

8. The multi-stage charge pump circuit of claim 1, wherein the first voltage output is configured to provide power to other circuits external to the multi-stage charge pump.

9. The multi-stage charge pump circuit of claim 1, wherein the inter-stage limitation circuit includes a small size resistor in series with a large size resistor.

10. The multi-stage charge pump circuit of claim 9, comprising an intermediary capacitor disposed between the small size resistor and the large size resistor.

11. An inter-stage limitation circuit, comprising:

a first capacitor to receive a charge from a first stage of a multi-stage charge pump;

a small size resistor to pass a current stored in the first capacitor;

a second capacitor to store a charge associated with a last stage of the multi-stage charge pump;

an intermediate capacitor to store an intermediate charge between the first capacitor and the second capacitor;

a large size resistor in series with the small size resistor; and

a PMOS transistor in parallel with the large size resistor, wherein the PMOS transistor is in an OFF state to enable the large size resistor and limit the current through the inter-stage limitation circuit.

12. The inter-stage limitation circuit of claim 11, wherein the first capacitor, second capacitor, and intermediate capacitor are arranged in parallel.

13. A method of operating a multi-stage charge pump, comprising:

ramping up a first voltage output of a first-stage charge pump;

ramping up a second voltage output of a last-stage charge pump in order to supply a voltage of an external switch;

limiting a current draw on the first voltage output by enabling a high resistance between the first voltage output of the first-stage charge pump and a first voltage input of the last-stage charge pump.

14. The method of claim 13, comprising switching off a PMOS transistor that is in parallel with the high resistance to enable the high resistance between the first stage and the last stage.

15. The method of claim 13, comprising switching on a PMOS transistor that is in parallel with the high resistance to disable the high resistance between the first stage and the last stage.

16. The method of claim 13, wherein the first voltage output is configured to provide power to other circuits.

17. The method of claim 13, comprising storing a first charge in a first capacitor adjacent an output of the first stage.

18. The method of claim 13, comprising storing a second charge in an intermediate capacitor between the first stage and the last stage.

19. The method of claim 13, comprising storing a second charge in a second capacitor adjacent an input of the last stage.

20. The method of claim 13, comprising storing and ramping up charge using a plurality of capacitors arranged in parallel.