MULTI-STAGE CHARGE PUMP WITH INTER-STAGE LIMITATION CIRCUIT
First Claim
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1. A multi-stage charge pump circuit, comprising:
- a first stage of the multi-stage charge pump having a first voltage output;
a last stage of the multi-stage charge pump having a first voltage input; and
an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.
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Abstract
A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.
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Citations
20 Claims
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1. A multi-stage charge pump circuit, comprising:
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a first stage of the multi-stage charge pump having a first voltage output; a last stage of the multi-stage charge pump having a first voltage input; and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An inter-stage limitation circuit, comprising:
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a first capacitor to receive a charge from a first stage of a multi-stage charge pump; a small size resistor to pass a current stored in the first capacitor; a second capacitor to store a charge associated with a last stage of the multi-stage charge pump; an intermediate capacitor to store an intermediate charge between the first capacitor and the second capacitor; a large size resistor in series with the small size resistor; and a PMOS transistor in parallel with the large size resistor, wherein the PMOS transistor is in an OFF state to enable the large size resistor and limit the current through the inter-stage limitation circuit. - View Dependent Claims (12)
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13. A method of operating a multi-stage charge pump, comprising:
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ramping up a first voltage output of a first-stage charge pump; ramping up a second voltage output of a last-stage charge pump in order to supply a voltage of an external switch; limiting a current draw on the first voltage output by enabling a high resistance between the first voltage output of the first-stage charge pump and a first voltage input of the last-stage charge pump. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification