ADAPTIVE SYNCHRONOUS RECTIFICATION IN A VOLTAGE CONVERTER

• US 20200136508A1
• Filed: 04/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bandyopadhyay, Saurav, Amaro, Michael G., DiRenzo, Michael Thomas, LaBella, Thomas Matthew, Neidorff, Robert Allan
• Granted Patent: US 11,018,582 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.

Claims

1. A circuit, comprising:

a first transistor;

a second transistor coupled to the first transistor at a switch node and to a ground node;

an estimator circuit configured to receive a first signal to control an on and off state of the first transistor, the estimator circuit configured to generate a second signal to control the on and off state of the second transistor, the second signal configured to have a pulse width based on a pulse width of the first signal; and

a clocked comparator including a clock input, a first input, and a second input, the first input configured to receive a voltage indicative of a voltage of the switch node, the second input coupled to a ground node, and the clock input is configured to receive a third signal indicative of the second signal, the clocked comparator configured to generate a comparator output signal;

wherein the estimator circuit is configured to adjust the pulse width of the second signal based on the comparator output signal.

2. The circuit of claim 1, wherein the second transistor includes a control input, and the clock input of the clocked comparator is coupled to the control input.

3. The circuit of claim 1, wherein the estimator circuit comprises a multiplier configured to determine an on-time for the second transistor based on an on-time of the first transistor.

4. The circuit of claim 3, wherein the multiplier comprises a Gilbert multiplier.

5. The circuit of claim 1, wherein the estimator circuit includes an averager circuit that is configured to receive the first signal and to generate an averager circuit output signal that is indicative of an average of the first signal.

6. The circuit of claim 1, wherein the estimator circuit includes:

a plurality of delay elements coupled in series, each of the delay elements of the plurality of delay elements including an output;

a logic gate coupled to the outputs of the plurality of delay elements, the logic gate including a logic gate output; and

an output circuit coupled to the logic gate output, the output circuit is configured to generate the second signal.

7. The circuit of claim 6, wherein each of the plurality of delay elements of the plurality of delay elements comprises an SR latch, and each SR latch includes an enable input.

8. The circuit of claim 7, wherein each enable input of each of the SR latches is configured to receive the first signal.

9. The circuit of claim 1, wherein the second transistor includes a control input, and the circuit further includes an arbiter circuit coupled between the estimator circuit and the control input, the arbiter circuit configured to receive a third signal to control an on and off state of the second transistor, and the arbiter circuit is configured to generate a voltage for the control input based on a timing relationship between the second and third signals.

10. The circuit of claim 1, wherein the circuit comprises a voltage regulator.

11. The circuit of claim 1, wherein the circuit comprises zero-voltage transition (ZVT) buck converter, and the first and second transistors comprise an auxiliary half bridge of the ZVT buck converter.

12. A circuit, comprising:

an estimator circuit configured to receive a first signal to control an on and off state of a first transistor, the estimator circuit configured to generate a second signal to control an on and off state of a second transistor, the second signal configured to have a pulse width based on a pulse width of the first signal; and

a clocked comparator including a clock input, a first input, and a second input, the first input configured to be coupled to a node between the first and second transistors, the second input coupled to a ground node, and the clock input coupled to receive a third signal indicative of the second signal, the clocked comparator configured to generate a comparator output signal responsive to a signal on the node between the first and second transistors;

wherein the estimator circuit is configured to adjust the pulse width of the second signal based on the comparator output signal.

13. The circuit of claim 12, wherein the estimator circuit comprises a multiplier configured to determine an on-time for the second transistor based on an on-time of the first transistor.

14. The circuit of claim 12, wherein the estimator circuit includes an averager circuit that is configured to receive the first signal and to generate an averager circuit output signal that is indicative of an average of the first signal.

15. The circuit of claim 12, wherein the estimator circuit includes:

a plurality of delay elements coupled in series, each of the delay elements of the plurality of delay elements including an output;

a logic gate coupled to the outputs of the plurality of delay elements, the logic gate including a logic gate output; and

an output circuit coupled to the logic gate output, the output circuit is configured to generate the second signal.

16. The circuit of claim 15, wherein:

each of the plurality of delay elements of the plurality of delay elements comprises an SR latch, and each SR latch includes an enable input; and

each enable input of each of the SR latches is configured to receive the first signal.

17. A method, comprising:

based on an on-time for a first transistor, determining an initial on-time for a second transistor;

turning off the second transistor using the determined on-time for the second transistor;

determining, using a clocked comparator, that a voltage on a node between the first and second transistors is not zero volts upon turning off the second transistor;

responsive to the voltage on the node determined not to be zero volts, changing the on-time for the second transistor.

18. The method of claim 17, wherein changing the on-time for the second transistor comprises increasing the on-time for the second transistor responsive to the voltage being greater than zero.

19. The method of claim 17, wherein changing the on-time for the second transistor comprises decreasing the on-time for the second transistor responsive to the voltage being less than zero.

20. The method of claim 17, wherein the first and second transistors are coupled to an inductor, and wherein determining the initial on-time for a second transistor includes determining the initial on-time based on:

the on-time for the first transistor;

a voltage across the inductor when the first transistor is on; and

the voltage across the inductor when the second transistor is on.