AUTOMATED SPEED RAMP CONTROL OF STEPPER MOTORS

• US 20200136539A1
• Filed: 01/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Curtis, Keith Edwin
• Granted Patent: US 11,323,052 B2
• Time in Patent Office: Days
• CPC Class Codes: G05B 19/40 Open loop systems, e.g. using stepping motor
• CPC Class Codes: G05B 19/416 characterised by control of velocity, acceleration or deceleration G05B19/19 takes precedence
• CPC Class Codes: G05B 2219/33088 Clock
• CPC Class Codes: G05B 2219/43139 VCO variable frequency oscillator or two oscilators with different frequency
• CPC Class Codes: H02P 8/14 Arrangements for controlling speed or speed and torque H02P8/12, H02P8/22 take precedence
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

Automated speed ramp control of stepper motor acceleration and deceleration using direct memory access (DMA) and core independent peripherals (CIPs) comprises a numerically controlled oscillator (NCO) controlled through direct memory access (DMA) transfers of prescale values used in combination with a clock oscillator to generate clock pulses that are a function of the clock oscillator frequency and the prescale values. This automates changing the frequency of the NCO, thereby controlling steeper motor speed, without requiring computer processing unit (CPU) overhead. The DMA module is enabled during a first number of clock pulses for step speed acceleration, disabled during a second number of clock pulses for normal operation at full step speed, and then re-enabled during a third number of clock pulses for step speed deceleration. A table in memory may store and provide a plurality of acceleration and deceleration prescale values for DMA transfers to the NCO.

Claims

1. A method for speed ramp control of a stepper motor using direct memory access (DMA) transfers, said method comprising the steps of:

providing a numerically controlled oscillator (NCO) having oscillator and prescale value inputs and an output providing clock pulses, wherein a frequency of the clock pulses is a function of the oscillator frequency and the prescale value;

providing a table of acceleration and deceleration prescale values in a memory;

programming the NCO with the acceleration prescale values from the memory using direct memory access (DMA) transfers for a first number of clock pulses;

inhibiting DMA transfers to the NCO for a second number of clock pulses; and

programming the NCO with the deceleration prescale values from the memory using the DMA transfers for a third number of clock pulses.

2. The method according to claim 1, further comprising the step of counting a certain number of clock pulses from the NCO before doing the DMA transfer to the NCO.

3. The method according to claim 1, further comprising the step of counting the number of clock pulses from the NCO then inhibiting the output of the NCO after the number of clock pulses reaches a maximum count.

4. An apparatus for automated speed ramp control of stepper motor acceleration and deceleration, comprising:

an oscillator having an output;

a numerically controlled oscillator (NCO) having oscillator and prescale value inputs and an output providing clock pulses, wherein the NCO oscillator input is coupled to the oscillator output and a frequency of the clock pulses from the NCO is a function of a frequency from the oscillator and the prescale value;

a memory for storing a plurality of acceleration and deceleration prescale values; and

a direct memory access (DMA) control circuit coupled between the NCO prescale value input and the memory, and the output of the NCO, wherein the DMA control circuit provides the NCO with the acceleration prescale values from the memory for a first number of clock pulses, inhibits the DMA control circuit for a second number of clock pulses, and then provides the NCO with the deceleration prescale values from the memory for a third number of clock pulses.

5. The apparatus according to claim 4, further comprising an accumulator counter coupled between the output of the NCO and the DMA control circuit, wherein the DMA control circuit provides a single prescale value to the NCO after a certain number of clock pulses have occurred.

6. The apparatus according to claim 4, further comprising a maximum counter coupled to the output of the NCO and inhibiting operation of the NCO after receiving a certain maximum number of clock pulses therefrom.

7. The apparatus according to claim 4, wherein the DMA control circuit comprises:

a pulse width modulation (PWM) module having an input coupled to the clock output of the NCO and an output; and

a data signal modulator (DSM) having a first input coupled to the clock output of the NCO, a second input coupled to a fixed logic level, an output coupled to a DMA trigger input of the DMA module and a control input coupled to the PWM module output for selectively coupling the output of the DSM between the first and second inputs thereof, wherein the first input is selected when the output of the PWM module is at a first logic level and the second input is selected when the output of the PWM module is at a second logic level.

8. The apparatus according to claim 7, further comprising an accumulator counter coupled between the output of the NCO, and the first input of the DSM and the input of the PWM module, wherein the DMA module provides a single prescale value to the NCO after a certain number of clock pulses have occurred.

9. The apparatus according to claim 7, wherein a duty cycle of the PWM module is programmable to provide the first logic level output during the first number of clock pulses, the second logic level output during the second number of clock pulses, and the first logic level output during the third number of clock pulses.

10. The apparatus according to claim 7, wherein the first logic level is a logic zero and the second logic level is a logic one.

11. The apparatus according to claim 7, wherein the first logic level is a logic one and the second logic level is a logic zero.

12. The apparatus according to claim 7, wherein the output of the DSM is configured to switch between the first and second inputs thereof on an edge of a control signal to the control input of the DSM.

13. The apparatus according to claim 4, wherein the DMA control circuit comprises:

a first counter for counting the first number of clock pulses;

a second counter for counting the second number of clock pulses;

a third counter for counting the third number of clock pulses; and

a multiplexer having a first input coupled to the NCO output, a second input coupled to a fixed logic level, an output coupled to the DMA module and input selection controlled by the first, second and third counters;

wherein

the first counter controls the multiplexer to couple the first input to the output thereof during the first number of clock pulses,

the second counter controls the multiplexer to couple the second input to the output thereof during the second number of clock pulses, and

the third counter controls the multiplexer to couple the first input to the output thereof during the third number of clock pulses.

14. An apparatus for automated speed ramp control of stepper motor acceleration and deceleration, comprising:

an oscillator having an output;

a numerically controlled oscillator (NCO) having oscillator and prescale value inputs and an output providing clock pulses, wherein the NCO oscillator input is coupled to the oscillator output and a frequency of the clock pulses is a function of a frequency from the oscillator and the prescale value;

a memory for storing a plurality of acceleration and deceleration prescale values;

a direct memory access (DMA) module coupled between the NCO prescale value input and the memory;

a pulse width modulation (PWM) module having an input coupled to the clock output of the NCO; and

a data signal modulator (DSM) having a first input coupled to the clock output of the NCO, a second input coupled to a fixed logic level, an output coupled to a DMA trigger input of the DMA module and a control input for selectively coupling the output of the DSM between the first and second inputs thereof;

wherein the DMA module programs the NCO with the acceleration prescale values during a first number of clock pulses, does no programming of the NCO during a second number of clock pulses, and programs the NCO with the deceleration prescale values during a third number of clock pulses.

15. The apparatus according to claim 14, further comprising an accumulator counter coupled between the clock output of the NCO, and the first input of the DSM and the input of the PWM module, wherein the DMA module provides a single prescale value to the NCO after a certain number of clock pulses have occurred.

16. The apparatus according to claim 14, further comprising a maximum counter coupled to the output of the NCO and inhibiting operation of the NCO after receiving a certain maximum number of clock pulses therefrom.

17. The apparatus according to claim 14, wherein a duty cycle of the PWM module is programmable to provide the first logic level output during the first number of clock pulses, the second logic level output during the second number of clock pulses, and the first logic level output during the third number of clock pulses.

18. The apparatus according to claim 14, wherein the output of the DSM is configured to switch between the first and second inputs thereof on an edge of a control signal to the control input of the DSM.