COMMON MODE OVERLOAD RECOVERY FOR AMPLIFIER

• US 20200136570A1
• Filed: 06/06/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: CHUANG, Shang-Yuan
• Granted Patent: US 10,826,443 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45356 the AAC comprising one or more op-amps, e.g. IC-blocks
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/213 in integrated circuits
• CPC Class Codes: H03F 3/303 using opamps as driving stages
• CPC Class Codes: H03F 3/45273 Mirror types
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

A circuit includes a first transistor having a first control input and first and current terminals. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal couples to the first current terminal at a first node. An output stage has a first input, a second input, and an output stage output. The first input couples to the fourth current terminal, and the second input couples to the second current terminal. A resistor has first and second resistor terminals. The first resistor terminal couples to the output stage output, and the second resistor terminal couples to the second control input. A third transistor has a third control input, a fifth current terminal, and a sixth current terminal. The fifth current terminal couples to the first resistor terminal, and the sixth current terminal couples to the second resistor terminal.

Claims

1. A circuit, comprising:

a first transistor having a first control input, a first current terminal, and a second current terminal;

a second transistor having a second control input, a third current terminal, and a fourth current terminal, the third current terminal coupled to the first current terminal at a first node;

an output stage having a first input, a second input, and an output stage output, the first input coupled to the fourth current terminal, and the second input coupled to the second current terminal;

a resistor having first and second resistor terminals, the first resistor terminal coupled to the output stage output, and the second resistor terminal coupled to the second control input; and

a third transistor having a third control input, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the first resistor terminal, and the sixth current terminal coupled to the second resistor terminal.

2. The circuit of claim 1, further comprising a fourth transistor having a fourth control input, a seventh current terminal, and an eighth current terminal, the fourth control input coupled to the first node, and the seventh current terminal coupled to the third control input.

3. The circuit of claim 2, further comprising:

a first current source device coupled to the first node, and

a second current source device coupled go the seventh current terminal.

4. The circuit of claim 3, wherein:

during a first mode of operation, a voltage on the second control input is configured to track a voltage on the first control input, and the third and fourth transistors are configured to be on; and

during a second mode operation, the voltages on the first and second control inputs become stuck at a first voltage, and the third and fourth transistors are configured to be off, thereby causing current to flow through the resistor and transition the circuit to the first mode of operation.

5. The circuit of claim 1, further comprising a first diode coupled between the first control input and the second control input, and comprising a second diode coupled between the first control input and the second control input.

6. The circuit of claim 1, wherein:

during a first mode of operation, a voltage on the second control input is configured to track a voltage on the first control input, and the third transistor is configured to be on; and

during a second mode operation, the voltages on the first and second control inputs become stuck at a first voltage, and the third transistor is configured to be off, thereby causing current to flow through the resistor and transition the circuit to the first mode of operation.

7. A circuit, comprising:

a first amplifier having an input and an output;

a current-to-voltage amplifier having an input; and

a first current mirror coupled between the output of the first amplifier and the input of the current-to-voltage amplifier;

the first amplifier including;

a first transistor having a first control input, a first current terminal, and a second current terminal;

a second transistor having a second control input, a third current terminal, and a fourth current terminal, the third current terminal coupled to the first current terminal at a first node;

an output stage having a first input, a second input, and an output stage output, the first input coupled to the fourth current terminal, and the second input coupled to the second current terminal;

a resistor having first and second resistor terminals, the first resistor terminal coupled to the output stage output, and the second resistor terminal coupled to the second control input; and

a third transistor having a third control input, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the first resistor terminal, and the sixth current terminal coupled to the second resistor terminal.

8. The circuit of claim 7, further comprising a fourth transistor having a fourth control input, a seventh current terminal, and an eighth current terminal, the fourth control input coupled to the first node, and the seventh current terminal coupled to the third control input.

9. The circuit of claim 8, further comprising:

a first current source device coupled to the first node, and

a second current source device coupled go the seventh current terminal.

10. The circuit of claim 9, wherein:

during a first mode of operation, a voltage on the second control input is configured to track a voltage on the first control input, and the third and fourth transistors are configured to be on; and

during a second mode operation, the voltages on the first and second control inputs become stuck at a first voltage, and the third and fourth transistors are configured to be off, thereby causing current to flow through the resistor and transition the circuit to the first mode of operation.

11. The circuit of claim 7, further comprising a first diode coupled between the first control input and the second control input, and comprising a second diode coupled between the first control input and the second control input.

12. The circuit of claim 7, wherein:

during a first mode of operation, a voltage on the second control input is configured to track a voltage on the first control input, and the third transistor is configured to be on; and

during a second mode operation, the voltages on the first and second control inputs become stuck at a first voltage, and the third transistor is configured to be off, thereby causing current to flow through the resistor and transition the circuit to the first mode of operation.

13. A circuit, comprising:

a first transistor having a first control input, a first current terminal, and a second current terminal;

a second transistor having a second control input, a third current terminal, and a fourth current terminal, the third current terminal coupled to the first current terminal at a first node;

an output stage having a first input, a second input, and an output stage output, the first input coupled to the fourth current terminal, and the second input coupled to the second current terminal;

a third transistor coupled to the output stage output and to the fourth current terminal; and

a resistor coupled to the output stage output and to the second control input;

responsive to a voltage on the second control input tracking a voltage on the first control input, the third transistor is configured to be on to cause current to flow through from the output stage output through the third transistor and to the second control input; and

responsive to the voltages on the first and second control inputs become stuck at a first voltage, the third transistor is configured to be off, thereby causing current to flow from the output stage output through a resistor to the second control input.

14. The circuit of claim 13, further comprising a fourth transistor having a fourth control input, a seventh current terminal, and an eighth current terminal, the fourth control input coupled to the first node, and the seventh current terminal coupled to the third control input.

15. The circuit of claim 14, further comprising:

a first current source device coupled to the first node, and

a second current source device coupled go the seventh current terminal.

16. The circuit of claim 14, wherein the first, second, and fourth transistors comprise p-type metal oxide semiconductor field effect transistors, and the third transistor comprises an n-type metal oxide semiconductor field effect transistor.

17. The circuit of claim 13, further comprising a first diode coupled between the first control input and the second control input, and comprising a second diode coupled between the first control input and the second control input.

18. The circuit of claim 13, wherein responsive to the voltage on the second control input tracking a voltage on the first control input, both the third and fourth transistors are configured to be on.

19. The circuit of claim 13, wherein responsive to the voltages on the first and second control inputs becoming stuck at the first voltage, both the third and fourth transistors are configured to be off.

20. The circuit of claim 13, wherein the output stage is a class AB output stage.