WIDEBAND POWER AMPLIFIER ARRANGEMENT

• US 20200136573A1
• Filed: 04/06/2017
• Published: 04/30/2020
• Est. Priority Date: 04/06/2017
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: HELLBERG, Richard
• Granted Patent: US 11,652,452 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 1/18 by use of distributed coupling , i.e. distributed amplifiers distributed amplifiers using coupling networks with distributed constants H03F3/605
• CPC Class Codes: H03F 2200/09 A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier
• CPC Class Codes: H03F 2200/315 the loading circuit of an amplifying stage comprising a transmission line
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 2200/522 the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/301 CMOS common drain output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/607 using FET's

Abstract

A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

Claims

1. A power amplifier arrangement for amplifying an input signal to produce an output signal comprising:

a plurality N of successive amplifier sections, wherein N=2, 3, or more;

a first input transmission line comprising multiple segments; and

a first output transmission line comprising multiple segments;

wherein

each amplifier section comprises one or more first transistors distributed along the first input transmission line and the first output transmission line such that gates of the one or more first transistors are connected to respective segments of the first input transmission line, drains of the one or more first transistors are connected to respective segments of the first output transmission line; and

wherein

each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal, and wherein

a portion of the input signal is one of N portions of the input signal partitioned on an amplitude basis, and

the output signal is produced at an end of the first output transmission line by building up N portions of the output signal from each amplifier section.

2. The power amplifier arrangement according to claim 1, wherein N portions of the input signal is partitioned by pre-shaping the N portions of the input signal by digital or analog shaping circuits before being input to each amplifier section.

3. The power amplifier arrangement according to claim 1, wherein lengths of the respective segments of the first output transmission line are non-equal.

4. The power amplifier arrangement according to claim 1, wherein each amplifier section further comprises one or more second transistors, and the power amplifier arrangement further comprises a second input transmission line comprising multiple segments and a second output transmission line comprising multiple segments, wherein gates of the one or more second transistors are connected to respective segments of the second input transmission line, drains of the one or more second transistors are connected to respective segments of the second output transmission line, and each amplifier section is configured to amplify a portion of positive input signal to produce a portion of positive output signal at the first output transmission line and to amplify a portion of negative input signal to produce a portion of negative output signal at the second output transmission line.

5. The power amplifier arrangement according to claim 4, further comprising a wideband coupler to combine positive and negative output signals from the first and second output transmission lines.

6. The power amplifier arrangement according to claim 4, wherein the one or more second transistors are the same type as the respective one or more first transistors and are connected in differential with the respective one or more first transistors.

7. The power amplifier arrangement according to claim 6, further comprising a negatively coupled inductor pair or a center-tapped inductor to feed Direct Current, DC, to the two differentially connected transistors.

8. The power amplifier arrangement according to claim 6, further comprising a balun or balanced-to-unbalanced transformer or a wideband 180-degree coupler to combine positive and negative output signals from the first and second output transmission lines.

9. The power amplifier arrangement according to claim 1, wherein each amplifier section further comprises one or more second transistors stacked with the respective one or more first transistors, and the power amplifier arrangement further comprises a second input transmission line comprising multiple segments, wherein gates of the one or more second transistors are connected to respective segments of the second input transmission line, drains of the one or more second transistors are connected to respective segments of the first output transmission line, and wherein each amplifier section is configured to amplify a portion of positive input signal and a portion of negative input signal to produce a portion of positive output signal and a portion of negative output signal at the first output transmission line.

10. An electronic device comprising a power amplifier arrangement according to claim 1.