FLIP FLOP
2 Assignments
0 Petitions
Accused Products
Abstract
Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.
3 Citations
43 Claims
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1-23. -23. (canceled)
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24. A flip flop circuit comprising:
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an input circuit configured to output an inverted output signal in response to an input signal; a master circuit configured to output a first master output signal on a first master output node based on the input signal and a clock signal, and to output a second master output signal on a second master output node based on the inverted output signal and the clock signal; a slave circuit including a first latch configured to output a first slave output signal on a first slave output node and a second slave output signal on a second slave output node based on the clock signal, a retention signal, and the first and second master output signals; and an output circuit configured to output an output signal in response to one of the first and second slave output signals, wherein the flip flop circuit is configured such that when the flip flop circuit is in a retention mode, the slave circuit maintains states of the first and second slave output signals irrespective of a state of the clock signal. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A flip flop circuit comprising:
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an input circuit configured to output an inverted output signal in response to an input signal; a master circuit including first cross-coupled inverters configured to output a first master output signal and a second master output signal based on the input signal, the inverted output signal, and a clock signal; a slave circuit including second cross-coupled inverters configured to output a first slave output signal and a second slave output signal based on the clock signal, a retention signal, and the first and second master output signals; and an output circuit configured to output an output signal in response to one of the first and second slave output signals, wherein the flip flop circuit is configured such that when the retention signal is either low or high, the slave circuit maintains states of the first and second slave output signals irrespective of a state of the clock signal. - View Dependent Claims (39, 40, 41)
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42. A flip flop circuit comprising:
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an input circuit connected to a first power, and configured to output an inverted output signal in response to an input signal; a master circuit connected to the first power, and configured to output a first master output signal and a second master output signal based on the input signal, the inverted output signal, and a clock signal; a slave circuit connected to a second power, and configured to output a first slave output signal and a second slave output signal based on the clock signal, a retention signal, and the first and second master output signals; and an output circuit connected to the first power, and configured to output an output signal in response to one of the first and second slave output signals, wherein the flip flop circuit is configured such that when the flip flop circuit is in a retention mode, the slave circuit maintains states of the first and second slave output signals irrespective of a state of the clock signal, wherein the flip flop circuit is configured that when the flip flop circuit is in a normal mode, the slave circuit outputs the first and second slave output signals based on the clock signal and first and second master output signals, and wherein the first power and the second power are higher than a ground voltage. - View Dependent Claims (43)
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Specification