SCHMITT TRIGGER CIRCUIT WITH INDEPENDENT CONTROL OVER HIGH AND LOW TRIP POINTS USING A SPLIT ARCHITECTURE

• US 20200136595A1
• Filed: 10/24/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Abandoned Application

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: GARG, Manish
• Application Number:
  US16/662,506
• Publication Number:
  US 20200136595A1
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 3/0377 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A Schmitt trigger circuit includes separate circuits for monitoring change in input signal voltage level in comparison to a low threshold to generate a change in logic state of a first control signal in response to a decrease in a voltage level of the input signal and in comparison to a high threshold to generate a change in logic state of a second control signal in response to an increase in the voltage level of the input signal. A first transistor has a source-drain path connected between a supply node and an output node, with a control terminal of the first transistor configured to receive the second control signal. A second transistor has a source-drain path connected between the output node and a ground node, with a control terminal of the second transistor configured to receive said first control signal.

Claims

1. A circuit, comprising:

a low threshold control circuit having an input that receives an input signal and an output the generates a first control signal, said low threshold control circuit configured to respond to a decrease in a voltage level of the input signal to be less than or equal to a low voltage trip point by changing a logic state of the first control signal;

a high threshold control circuit having an input that receives the input signal and an output the generates a second control signal, said high threshold control circuit configured to respond to an increase in the voltage level of the input signal to be greater than or equal to a high voltage trip point by changing a logic state of the second control signal;

a first transistor having a source-drain path connected between a supply node and an output node, said first transistor having a control terminal configured to receive said second control signal; and

a second transistor having a source-drain path connected between the output node and a ground node, said second transistor having a control terminal configured to receive said first control signal.

2. The circuit of claim 1, further comprising a latch circuit having a first latch node connected to the output node.

3. The circuit of claim 2, wherein the latch circuit comprises:

a first inverter circuit having an input connected to the output node; and

a second inverter circuit having an output connected to the output node;

wherein an output of the first inverter circuit is connected to an input of the second inverter circuit.

4. The circuit of claim 1, wherein the high voltage trip point is greater than the low voltage trip point.

5. The circuit of claim 1, wherein the first control signal changes logic state from a first logic state to a second logic state when the voltage level of the input signal decreases to be less than or equal to the low voltage trip point and wherein the second control signal changes from the first logic state to the second logic state when the voltage level of the input signal decreases to be less than or equal to a first voltage, said first voltage being greater than the low voltage trip point.

6. The circuit of claim 5, wherein the first logic state is logic low, the second logic state is logic high, the first transistor is a p-channel MOSFET and the second transistor is an n-channel MOSFET.

7. The circuit of claim 1, wherein the second control signal changes logic state from a second logic state to a first logic state when the voltage level of the input signal increases to be greater than or equal to the high voltage trip point and wherein the first control signal changes from the second logic state to the first logic state when the voltage level of the input signal increases to be greater than or equal to a second voltage, said second voltage being less than the high voltage trip point.

8. The circuit of claim 7, wherein the first logic state is logic low, the second logic state is logic high, the first transistor is a p-channel MOSFET and the second transistor is an n-channel MOSFET.

9. The circuit of claim 1, wherein the low threshold control circuit comprises:

a first p-channel transistor having a gate terminal configured to receive the input signal;

a second p-channel transistor having a gate terminal configured to receive the input signal;

an n-channel transistor having a gate terminal configured to receive the input signal;

wherein source-drain paths of the first p-channel transistor, the second p-channel transistor and the n-channel transistor are connected in series; and

wherein the first control signal is generated at drains of the second p-channel transistor and the n-channel transistor connected to the output of the low threshold control circuit.

10. The circuit of claim 9, wherein the low threshold control circuit further comprises a feedback transistor having a source-drain path connected between a ground node and a node between the first p-channel transistor and the second p-channel transistor, said feedback transistor having a control terminal configured to receive the first control signal.

11. The circuit of claim 1, wherein the high threshold control circuit comprises:

a p-channel transistor having a gate terminal configured to receive the input signal;

a first n-channel transistor having a gate terminal configured to receive the input signal;

a second n-channel transistor having a gate terminal configured to receive the input signal;

wherein source-drain paths of the p-channel transistor, the first n-channel transistor and the second n-channel transistor are connected in series; and

wherein the second control signal is generated at drains of the p-channel transistor and the first n-channel transistor connected to the output of the high threshold control circuit.

12. The circuit of claim 11, wherein the high threshold control circuit further comprises a feedback transistor having a source-drain path connected between a power supply node and a node between the first n-channel transistor and the second n-channel transistor, said feedback transistor having a control terminal configured to receive the second control signal.

13. A method, comprising:

driving a gate terminal of an n-channel MOSFET with a first control signal;

driving a gate terminal of a p-channel MOSFET with a second control signal;

wherein drains of the n-channel MOSFET and the p-channel MOSFET are connected to an output node generating an output signal;

in response to a decrease in a voltage level of an input signal to be less than or equal to a low voltage trip point, changing a logic state of the first control signal; and

in response to an increase in the voltage level of the input signal to be greater than or equal to a high voltage trip point, changing a logic state of the second control signal.

14. The method of claim 13, wherein the high voltage trip point is greater than the low voltage trip point.

15. The method of claim 13, further comprising latching a logic state of the output signal.

16. The method of claim 13, wherein changing the logic state of the first control signal comprises changing the logic state of the first control signal from a first logic state to a second logic state when the voltage level of the input signal decreases to be less than or equal to the low voltage trip point;

and further comprising;

changing the logic state of the second control signal from the first logic state to the second logic state when the voltage level of the input signal decreases to be less than or equal to a first voltage, said first voltage being greater than the low voltage trip point.

17. The method of claim 16, wherein the first logic state is logic low and the second logic state is logic high.

18. The method of claim 13, wherein changing the logic state of the second control signal comprises changing the logic state of the second control signal from a second logic state to a first logic state when the voltage level of the input signal increases to be greater than or equal to the high voltage trip point;

and further comprising;

changing the logic state of the first control signal from the second logic state to the first logic state when the voltage level of the input signal increases to be greater than or equal to a second voltage, said second voltage being less than the high voltage trip point.

19. The method of claim 18, wherein the first logic state is logic low and the second logic state is logic high.

20. A circuit, comprising:

a low threshold control circuit comprising;

a first p-channel transistor having a gate terminal configured to receive an input signal;

a second p-channel transistor having a gate terminal configured to receive the input signal;

a first n-channel transistor having a gate terminal configured to receive the input signal;

wherein source-drain paths of the first p-channel transistor, the second p-channel transistor and the first n-channel transistor are connected in series; and

wherein a first control signal is generated at a first node that is connected to drains of the second p-channel transistor and the first n-channel transistor;

a high threshold control circuit comprising;

a third p-channel transistor having a gate terminal configured to receive the input signal;

a second n-channel transistor having a gate terminal configured to receive the input signal;

a third n-channel transistor having a gate terminal configured to receive the input signal;

wherein source-drain paths of the third p-channel transistor, the second n-channel transistor and the third n-channel transistor are connected in series; and

wherein the second control signal is generated at a second node connected to drains of the third p-channel transistor and the second n-channel transistor;

a fourth p-channel transistor having a source-drain path connected between a supply node and an output node, said fourth p-channel transistor having a control terminal configured to receive said second control signal; and

a fourth n-channel transistor having a source-drain path connected between the output node and a ground node, said fourth n-channel transistor having a control terminal configured to receive said first control signal.

21. The circuit of claim 20, further comprising a latch circuit having a first latch node connected to the output node.

22. The circuit of claim 21, wherein the latch circuit comprises:

a first inverter circuit having an input connected to the output node; and

a second inverter circuit having an output connected to the output node;

wherein an output of the first inverter circuit is connected to an input of the second inverter circuit.

23. The circuit of claim 20:

wherein the low threshold control circuit further comprises a first feedback transistor having a source-drain path connected between the ground node and a node between the first p-channel transistor and the second p-channel transistor, said first feedback transistor having a control terminal configured to receive the first control signal; and

wherein the high threshold control circuit further comprises a second feedback transistor having a source-drain path connected between the supply node and a node between the third n-channel transistor and the fourth n-channel transistor, said second feedback transistor having a control terminal configured to receive the second control signal.