SCHMITT TRIGGER CIRCUIT WITH INDEPENDENT CONTROL OVER HIGH AND LOW TRIP POINTS USING A SPLIT ARCHITECTURE
First Claim
1. A circuit, comprising:
- a low threshold control circuit having an input that receives an input signal and an output the generates a first control signal, said low threshold control circuit configured to respond to a decrease in a voltage level of the input signal to be less than or equal to a low voltage trip point by changing a logic state of the first control signal;
a high threshold control circuit having an input that receives the input signal and an output the generates a second control signal, said high threshold control circuit configured to respond to an increase in the voltage level of the input signal to be greater than or equal to a high voltage trip point by changing a logic state of the second control signal;
a first transistor having a source-drain path connected between a supply node and an output node, said first transistor having a control terminal configured to receive said second control signal; and
a second transistor having a source-drain path connected between the output node and a ground node, said second transistor having a control terminal configured to receive said first control signal.
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Accused Products
Abstract
A Schmitt trigger circuit includes separate circuits for monitoring change in input signal voltage level in comparison to a low threshold to generate a change in logic state of a first control signal in response to a decrease in a voltage level of the input signal and in comparison to a high threshold to generate a change in logic state of a second control signal in response to an increase in the voltage level of the input signal. A first transistor has a source-drain path connected between a supply node and an output node, with a control terminal of the first transistor configured to receive the second control signal. A second transistor has a source-drain path connected between the output node and a ground node, with a control terminal of the second transistor configured to receive said first control signal.
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Citations
23 Claims
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1. A circuit, comprising:
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a low threshold control circuit having an input that receives an input signal and an output the generates a first control signal, said low threshold control circuit configured to respond to a decrease in a voltage level of the input signal to be less than or equal to a low voltage trip point by changing a logic state of the first control signal; a high threshold control circuit having an input that receives the input signal and an output the generates a second control signal, said high threshold control circuit configured to respond to an increase in the voltage level of the input signal to be greater than or equal to a high voltage trip point by changing a logic state of the second control signal; a first transistor having a source-drain path connected between a supply node and an output node, said first transistor having a control terminal configured to receive said second control signal; and a second transistor having a source-drain path connected between the output node and a ground node, said second transistor having a control terminal configured to receive said first control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method, comprising:
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driving a gate terminal of an n-channel MOSFET with a first control signal; driving a gate terminal of a p-channel MOSFET with a second control signal; wherein drains of the n-channel MOSFET and the p-channel MOSFET are connected to an output node generating an output signal; in response to a decrease in a voltage level of an input signal to be less than or equal to a low voltage trip point, changing a logic state of the first control signal; and in response to an increase in the voltage level of the input signal to be greater than or equal to a high voltage trip point, changing a logic state of the second control signal. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A circuit, comprising:
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a low threshold control circuit comprising; a first p-channel transistor having a gate terminal configured to receive an input signal; a second p-channel transistor having a gate terminal configured to receive the input signal; a first n-channel transistor having a gate terminal configured to receive the input signal; wherein source-drain paths of the first p-channel transistor, the second p-channel transistor and the first n-channel transistor are connected in series; and wherein a first control signal is generated at a first node that is connected to drains of the second p-channel transistor and the first n-channel transistor; a high threshold control circuit comprising; a third p-channel transistor having a gate terminal configured to receive the input signal; a second n-channel transistor having a gate terminal configured to receive the input signal; a third n-channel transistor having a gate terminal configured to receive the input signal; wherein source-drain paths of the third p-channel transistor, the second n-channel transistor and the third n-channel transistor are connected in series; and wherein the second control signal is generated at a second node connected to drains of the third p-channel transistor and the second n-channel transistor; a fourth p-channel transistor having a source-drain path connected between a supply node and an output node, said fourth p-channel transistor having a control terminal configured to receive said second control signal; and a fourth n-channel transistor having a source-drain path connected between the output node and a ground node, said fourth n-channel transistor having a control terminal configured to receive said first control signal. - View Dependent Claims (21, 22, 23)
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Specification