CLOCK GENERATION CIRCUIT AND CLOCK ADJUSTMENT METHOD THEREOF
First Claim
1. A clock generation circuit, comprising:
- a fixed clock source generating a reference clock signal having a fixed frequency;
a variable clock source receiving a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency;
a timing adjustment circuit coupled to the fixed clock source and the variable clock source to receive the reference clock signal and the operational clock signal, determining whether a frequency of the operational clock signal is N times of a target frequency according to the reference clock signal, providing the changed frequency setting signal to the variable clock source to change the frequency of the operational clock signal when the frequency of the operational clock signal is not N times of the target frequency, and maintaining a frequency of the current operational clock signal when the frequency of the operational clock signal is N times of the target frequency, wherein N is an integer greater than one; and
a pulse width signal generator coupled to the variable clock source to receive the operational clock signal, and dividing the frequency of the operational clock signal to generate a pulse width modulation signal having the target frequency.
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Accused Products
Abstract
A clock generation circuit and a clock adjustment method thereof are provided. The clock generation circuit includes a fixed clock source, a variable clock source, a timing adjustment circuit, and a pulse width signal generator. The fixed clock source generates a reference clock signal having a fixed frequency. The variable clock source receives a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency. The timing adjustment circuit determines whether a frequency of the operation clock signal is N times of a target frequency according to the reference clock signal to set a frequency of the operation clock signal. The pulse width signal generator divides the operating clock signal to generate a pulse width modulation signal having the target frequency.
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Citations
18 Claims
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1. A clock generation circuit, comprising:
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a fixed clock source generating a reference clock signal having a fixed frequency; a variable clock source receiving a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency; a timing adjustment circuit coupled to the fixed clock source and the variable clock source to receive the reference clock signal and the operational clock signal, determining whether a frequency of the operational clock signal is N times of a target frequency according to the reference clock signal, providing the changed frequency setting signal to the variable clock source to change the frequency of the operational clock signal when the frequency of the operational clock signal is not N times of the target frequency, and maintaining a frequency of the current operational clock signal when the frequency of the operational clock signal is N times of the target frequency, wherein N is an integer greater than one; and a pulse width signal generator coupled to the variable clock source to receive the operational clock signal, and dividing the frequency of the operational clock signal to generate a pulse width modulation signal having the target frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A clock adjustment method of a clock generation circuit, comprising:
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receiving a reference clock signal having a fixed frequency via a timing adjustment circuit; receiving an operational clock signal having a variable frequency generated according to a frequency setting signal via the timing adjustment circuit; determining whether a frequency of the operational clock signal is N times of a target frequency according to the reference clock signal via the timing adjustment circuit, wherein N is an integer greater than one; when the frequency of the operational clock signal is not N times of the target frequency, providing the changed frequency setting signal to a variable clock source via the timing adjustment circuit to change the frequency of the operational clock signal; when the frequency of the operational clock signal is N times of the target frequency, continuously providing the current frequency setting signal to the variable clock source via the timing adjustment circuit to maintain the frequency of the operational clock signal; and dividing the frequency of the operational clock signal via a pulse width signal generator to generate a pulse width modulation signal having the target frequency. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification