DUTY CYCLE MONITOR CIRCUIT AND METHOD FOR DUTY CYCLE MONITORING

• US 20200136599A1
• Filed: 10/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: SAVARY, Pierre, Pavao Moreira, Cristian, Bouchayer, Matthis, Vigier, Jean-Stephane
• Granted Patent: US 10,700,672 B2
• Time in Patent Office: Days
• CPC Class Codes: G01S 13/931 of land vehicles
• CPC Class Codes: G01S 7/032 Constructional details for solid-state radar subsystems
• CPC Class Codes: G01S 7/4004 of parts of a radar system
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.

Claims

1. An electronic system comprising:

a clock generation circuit configured to generate a clock signal; and

a duty cycle monitoring circuit, DTC, operably coupled to the clock generation circuit and configured to monitor a duty cycle of the generated clock signal;

wherein the communication unit is characterized in that;

the DTC comprises;

a differential signal generator configured to receive the generated clock signal and generate an inverted representation of the generated clock signal, and generate a non-inverted representation of the generated clock signal;

an averaging circuit operably coupled to the differential signal generator and configured to average the generated non-inverted clock signal and average the inverted representation of the generated clock signal;

a comparison circuit comprising at least a first comparator configured to receive and compare the averaged non-inverted generated clock signal with a second respective reference voltage threshold and a second comparator configured to receive and compare the averaged inverted representation with a first respective reference voltage threshold;

a reference voltage generation circuit operably coupled to the averaging circuit and configured to provide the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provide the second respective reference voltage threshold associated with the averaged non-inverted representation of the generated clock signal; and

a summing circuit operably coupled to the comparison circuit and configured to sum outputs of the first comparator and second comparator wherein an output of the summing circuit comprises a monitored duty cycle of the generated clock signal.

2. The electronic system of claim 1 wherein the generated clock signal is a single ended clock signal and the comparison circuit and reference voltage generation circuit is formed by cross connected reference voltages with the comparison circuit configured to perform a differential comparison of an averaged generated clock signal with a respective reference voltage threshold.

3. The electronic system of claim 2 wherein the comparison circuit being configured to perform a differential comparison of an averaged generated clock signal with a respective reference voltage threshold that removes single ended DTC variations of the generated clock signal over one or more of process, voltage, temperature, PVT, variations.

4. The electronic system of claim 1 wherein the reference voltage generation circuit comprises at least two sets of resistor ladders configured to provide a fixed reference voltage threshold to respective comparator inputs.

5. The electronic system of claim 1 wherein the differential signal generator circuit is configured to transform a received single-ended generated clock signal into a differential DTC signal on a non-inverted clock signal path and an inverted clock signal path of the DTC.

6. The electronic system of claim 4 wherein a first fixed reference voltage threshold generated on a clock signal path is directly proportional to a DTC signal in a non-inverted clock signal path, and a second fixed reference voltage threshold generated on an inverted clock signal path is directly proportional to a signal DTC in the inverted clock signal path and inversely proportional to the DTC signal in the non-inverted clock signal path.

7. The electronic system of claim 1 wherein the averaging circuit averages the generated clock signal and averages the inverted representation of the generated clock signal by converting the clock pulses into a varying DC voltage.

8. The electronic system of claim 1 wherein the averaging circuit is a resistor-capacitor filter.

9. The electronic system of claim 1 wherein the electronic system comprises at least one master device and at least one slave device, where the master device generates a master system clock signal to distribute to other devices including the at least one slave device, where the at least one master device comprises a reference phase locked loop, PLL, circuit arranged to generate the clock signal.

10. The electronic system of claim 9 wherein each of the at least one master device and at least one slave device comprises a receive clock signal demodulator configured to receive the distributed master system clock signal and re-create a system clock signal, and each of the at least one master device and at least one slave device is coupled to the DTC that is configured to monitor a respective re-created system clock signal.

11. The electronic system of claim 1 wherein the electronic system is a communication unit.

12. A duty cycle monitoring circuit, DTC, configured to receive and monitor a duty cycle of a generated clock signal;

wherein the DTC is characterized by;

a differential signal generator configured to receive the generated clock signal and generate an inverted representation of the generated clock signal, and generate a non-inverted representation of the generated clock signal;

an averaging circuit operably coupled to the differential signal generator and configured to average the generated non-inverted clock signal and average the inverted representation of the generated clock signal;

a comparison circuit comprising at least a first comparator configured to receive and compare the averaged non-inverted generated clock signal with a second respective reference voltage threshold and a second comparator configured to receive and compare the averaged inverted representation with a first respective reference voltage threshold;

a reference voltage generation circuit operably coupled to the averaging circuit and configured to provide the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provide the second respective reference voltage threshold associated with the averaged non-inverted representation of the generated clock signal; and

a summing circuit operably coupled to the comparison circuit and configured to sum outputs of the first comparator and second comparator wherein an output of the summing circuit comprises a monitored duty cycle of the generated clock signal.

13. A method for monitoring a duty cycle of a clock signal, wherein the method comprises, at a duty cycle monitoring circuit, DTC:

receiving a generated clock signal;

generating, in a differential signal generator circuit, an inverted representation and a non-inverted representation of the generated clock signal;

averaging, in an averaging circuit, the inverted representation of the generated clock signal;

averaging, in an averaging circuit, the non-inverted representation of the generated clock signal;

generating a second respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and comparing, in a comparison circuit, the averaged non-inverted representation of the clock signal with the second respective reference voltage threshold in a first comparator;

generating, in a reference voltage generation circuit, a first respective reference voltage threshold associated with the filtered non-inverted representation of the generated clock signal, and comparing the first respective reference voltage threshold with the averaged inverted representation of the clock signal in a second comparator; and

summing outputs of the first and second comparators to generate a monitored duty cycle of the generated clock signal.

14. The method of claim 13 wherein the generated clock signal is a single ended clock signal and the comparison circuit and reference voltage generation circuit is formed by cross connected reference voltages with the comparison circuit configured to perform a differential comparison of an averaged generated clock signal with a respective reference voltage threshold.

15. The method of claim 14 wherein the comparison circuit performs a differential comparison of an averaged generated clock signal with a respective reference voltage threshold that removes single ended DTC variations of the generated clock signal over one or more of process, voltage, temperature, PVT, variations.

16. The method of claim 13 wherein the reference voltage generation circuit comprises at least two sets of resistor ladders configured to provide a fixed reference voltage threshold to respective comparator inputs.

17. The method of claim 13 wherein the differential signal generator circuit transforms a received single-ended generated clock signal into a differential DTC signal on a non-inverted clock signal path and an inverted clock signal path of the DTC.

18. The method of claim 17 wherein a first fixed reference voltage threshold generated on a clock signal path is directly proportional to a DTC signal in a non-inverted clock signal path, and a second fixed reference voltage threshold generated on an inverted clock signal path is directly proportional to a signal DTC in the inverted clock signal path and inversely proportional to the DTC signal in the non-inverted clock signal path.

19. The method of claim 13 further comprising averaging the generated clock signal and averaging the inverted representation of the generated clock signal by converting the clock pulses into a varying DC voltage.

20. The method of claim 13 wherein the averaging circuit is a resistor-capacitor filter.