REFERENCE VOLTAGE CIRCUIT AND POWER-ON RESET CIRCUIT

• US 20200136606A1
• Filed: 10/14/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Inventors: WATANABE, Kotaro, Singh, Sukhwinder
• Granted Patent: US 10,819,335 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A reference voltage circuit includes a first output terminal from which a first reference voltage is supplied; a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source; a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.

Claims

1. A reference voltage circuit, comprising:

a first output terminal from which a first reference voltage is supplied;

a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source;

a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and

a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.

2. The reference voltage circuit according to claim 1, wherein the first voltage drop circuit is configured by a third MOS transistor of a depletion type, the third MOS transistor containing a gate connected to the source of the first MOS transistor, a drain connected to the source of the first MOS transistor and the gate of the third MOS transistor, and a source connected to the first output terminal.

3. The reference voltage circuit according to claim 1, further comprising:

a second output terminal from which a second reference voltage is supplied;

a fourth MOS transistor of a depletion type, the fourth MOS transistor containing a drain connected to a power supply terminal, a gate connected to the first output terminal, and a source;

a second voltage drop circuit including a first end connected to the source of the fourth MOS transistor and a second end connected to the second output terminal; and

a fifth MOS transistor of a depletion type, the fifth MOS transistor containing a drain connected to the second output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.

4. The reference voltage circuit according to claim 3, wherein the second voltage drop circuit is configured by a sixth MOS transistor of a depletion type, the sixth MOS transistor containing a gate connected to the source of the fourth MOS transistor, a drain connected to the source of the fourth MOS transistor and the gate of the sixth MOS transistor, and a source connected to the second output terminal.

5. A power-on reset circuit, comprising:

the reference voltage circuit of claim 1; and

a reset signal output circuit configured to provide a reset signal based on a result of comparison between the first reference voltage supplied by the reference voltage circuit and a power supply voltage applied to the power supply terminal.