METHOD FOR CONTROLLING A SWITCH MODULE BASED ON THYRISTOR SWITCHING ELEMENTS

• US 20200136607A1
• Filed: 11/15/2017
• Published: 04/30/2020
• Est. Priority Date: 11/23/2016
• Status: Active Grant

• Current Assignee: Maschinenfabrik Reinhausen GmbH (Richard Scheubeck Beteiligungs-Gmbh & Co. KG)
• Original Assignee: Maschinenfabrik Reinhausen GmbH (Richard Scheubeck Beteiligungs-Gmbh & Co. KG)
• Inventors: Engel, Stefan, de Doncker, W. Rik
• Granted Patent: US 10,727,755 B2
• Time in Patent Office: Days
• CPC Class Codes: H01F 29/04 having provision for tap-changing without interrupting the load current
• CPC Class Codes: H02M 1/081 wherein the phase of the control voltage is adjustable with reference to the AC source
• CPC Class Codes: H02M 5/12 for conversion of voltage or current amplitude only
• CPC Class Codes: H02M 5/2573 with control circuit

Abstract

A method of controlling at least one switching module having commutation cells which are associated with a regulating winding of a regulating transformer, the commutation cells including: a first and second switching element each having two thyristors in antiparallel connection.

Claims

1. A method of controlling at least one switching module comprising a first commutation cell and a second commutation cell, which are each associated with a regulating winding of a regulating transformer by way of a first terminal and a second terminal, wherein each of the at least one switching module is provided with a feed-in line and a feed-out line and wherein the first commutation cell and the second commutation cell comprise:

a first switching element having two thyristors in antiparallel connection; and

a second switching element having two thyristors in antiparallel connection;

wherein the method comprises;

determining a tap voltage, which is present between the first terminal and the second terminal and represents a voltage across the regulating winding of the regulating transformer;

determining an induced voltage representing the induced voltage in the regulating winding;

detecting a load current flowing from the feed-out line of the commutation cell;

determining a phase displacement φ

between the load current and the tap voltage;

after receipt of a commutation command for commutation of a current from the first switching element to the second switching element then in accordance with a first commutation strategy a first check is carried out, wherein the first check comprises;

determining whether the phase displacement between the load current and the tap voltage lies outside a limit range, and

evaluating the result of the first check as positive when the phase displacement φ

lies outside the limit range;

a second check is carried out, wherein the second check comprises;

determining whether a time to a next anticipated zero transition of the tap voltage is greater than a commutation time period and that the result is evaluated as positive if this is the case;

if the first check and the second checks are positive, the commutation process is prepared in a step in that a first thyristor of the two thyristors belonging to the first switching element and lying in a blocking direction with respect to the induced voltage is deactivated and a second thyristor of the two thyristors belonging to the second switching element and lying in a blocking direction with respect to the tap voltage is activated; and

after the preparation of the commutation process, then in another step;

as long as the time to the anticipated next zero transition of the tap voltage is greater than the commutation time period, a third check is carried out as to whether the first thyristor has become free and the third check is evaluated as positive if this is the case; and

if the third check is evaluated as positive, the commutation is initiated in a step in that a third thyristor of the two thyristors belonging to the second switching element and lying antiparallel to the second thyristor is activated, and a fourth thyristor of the two thyristors belonging to the first switching element and lying antiparallel to the first thyristor is deactivated; and

if the first check and/or the second check is/are not evaluated as positive, no commutation is initiated, or if the third check is not evaluated as positive the commutation in accordance with the first commutation strategy is broken off.

2. The method according to claim 1, wherein the commutation is broken off in that the second thyristor is deactivated and the first thyristor is activated.

3. The method according to claim 1, wherein after the step for preparation of the commutation process:

as long as the time to the anticipated next zero transition of the tap voltage is greater than the commutation time period, a fourth check is carried out as to whether the amount of the induced voltage falls below a limit value of the tap voltage and the result is evaluated as positive if this is the case;

if the result of the third check and that of the fourth check are evaluated as positive, the commutation is initiated; and

otherwise the commutation is broken off in that the second thyristor is deactivated and the first thyristor is activated.

4. The method according to claim 1, wherein:

if the commutation in accordance with the first commutation strategy has been broken off more often than a predetermined number, and/or if the phase displacement between load current and the tap voltage lies within the limit range;

the commutation in accordance with second commutation process is carried out, wherein;

after receipt of the commutation command;

a trigger instant is waited out in a waiting step;

the fourth thyristor is deactivated and the third thyristor is activated in a step) when the trigger instant is reached; and

the first thyristor is deactivated and the second thyristor activated in a step after the zero transition of the tap voltage.

5. The method according to claim 4, wherein:

the trigger instant is determined in accordance with a function of a hold-off interval of the thyristors and the maximum current load resulting from the second commutation strategy.

6. The method according to claim 1, wherein the commutation time period corresponds with a sum of an overlap time and a hold-off interval of the first thyristor, the second thyristor, the third thyristor, or the fourth thyristor.

7. The method according to claim 1, wherein an overlap time depends on a trigger angle and the load current and describes a time in which both the first switching element and the second switching element of a commutation cell are conductive during the commutation process.

8. The method according to claim 1, wherein;

φ

cap<

φ

≤

0,

wherein φ

cap<

0,

for the limit range of the phase displacement φ

between load current and tap voltage.

9. The method according to claim 1, wherein

at least one of the first thyristor, the second thyristor, the third thyristor, or the fourth thyristor is activated, when a gate terminal thereof is driven, so as to enable triggering and

at least one of the first thyristor, the second thyristor, the third thyristor, or the fourth thyristor is deactivated, when the gate terminal thereof is not driven, so as to prevent triggering.

10. A non-volatile, computer readable medium comprising computer executable instructions, which when executed causes a controller to execute a method according to claim 1.