DOUBLE GATE TRANSISTOR DEVICE AND METHOD OF OPERATING

• US 20200136608A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 02/29/2016
• Status: Active Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Bina, Markus, Barrenscheen, Jens, Mauder, Anton
• Application Number:
  US16/722,809
• Publication Number:
  US 20200136608A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7606 Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2017/6878 using multi-gate field-effect transistors

Abstract

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Claims

1. A transistor device comprising:

a semiconductor body with a first semiconductor layer comprising a first type of group III nitride and a second semiconductor layer adjoining the first semiconductor layer and comprising a second type of group III nitride;

a source electrode connected to the first semiconductor layer and the second semiconductor layer;

a drain electrode spaced apart from the source electrode and connected to the first semiconductor layer and the second semiconductor layer; and

a first gate electrode and a second gate electrode that are spaced apart in a current flow direction of the transistor device.

2. The transistor device of claim 1, wherein the semiconductor body further comprises a third semiconductor layer adjoining the second semiconductor layer and comprising a group III nitride, and wherein at least one of the first gate electrode and the second gate electrode adjoins the third semiconductor layer and is separated from the second semiconductor layer by the third semiconductor layer.

3. The transistor device of claim 1, wherein at least one of the first gate electrode and the second gate electrode extends through the second semiconductor layer into the first semiconductor layer and is dielectrically insulated from the second semiconductor layer and the first semiconductor layer by a gate dielectric.

4. The transistor device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises a doped semiconductor layer.

5. The transistor device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer comprises an intrinsic semiconductor layer.

6. The transistor device of claim 5, wherein the semiconductor body further comprises at least one third semiconductor layer adjoining the second semiconductor layer and comprising a doped group III nitride, and wherein at least one of the first gate electrode and the second gate electrode adjoins the at least one third semiconductor layer and is separated from the second semiconductor layer by the third semiconductor layer.

7. The transistor device of claim 6, wherein the first gate electrode adjoins the at least one third semiconductor layer, and wherein the second gate electrode adjoins the second semiconductor layer.

8. The transistor device of claim 1, further comprising a field electrode adjoining the second gate electrode.

9. The transistor device of claim 1, wherein the second gate electrode is electrically connected with the source electrode.

10. The transistor device of claim 1, wherein the first type of group III nitride comprises gallium nitride (GaN), and wherein the second type of group III nitride comprises aluminum gallium nitride (AlGaN).

11. A method comprising:

switching off a transistor device by interrupting a first conducting channel by driving a first gate electrode and, after interrupting the first conducting channel, interrupting a second conducting channel by driving a second gate electrode, wherein the second gate electrode is arranged adjacent the first gate electrode in a current flow direction of the transistor device.

12. The method of claim 11, wherein the transistor device comprises a field-effect controlled transistor device, wherein interrupting the first conducting channel comprises interrupting the first conducting channel in a body region, wherein interrupting the second conducting channel comprises interrupting the second conducting channel in the body region, wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric, wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, wherein the second gate electrode is separated from the first gate electrode by a separation layer, and wherein the body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

13. The method of claim 11, wherein the transistor device comprises a HEMT device, a normally-on HEMT device, or a normally-off HEMT device.

14. The method of claim 11, wherein the transistor device comprises a GIT device.

15. The method of claim 14, wherein the GIT device comprises a first injection gate adjoining the first gate electrode and a second injection gate adjoining the second gate electrode.

16. The method of claim 14, wherein the GIT device comprises only one injection gate.

17. The method of claim 12, wherein driving the first gate electrode comprises decreasing a first drive signal from a first on-level to a first off-level, and wherein driving the second gate electrode comprises decreasing a second drive signal between the second gate electrode and the source region from a second on-level to a second off-level.

18. The method of claim 17, wherein driving the first gate electrode comprises clamping the second gate electrode to the second on-level.

19. The method of claim 17, wherein the second off-level is different from the first off-level.