SWITCH CIRCUIT AND HIGH-SPEED MULTIPLEXER-DEMULTIPLEXER

• US 20200136609A1
• Filed: 10/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Lontium Semiconductor Corporation
• Original Assignee: Lontium Semiconductor Corporation
• Inventors: TAO, Cheng, XIA, Hongfeng, CHEN, Yu, JI, Xiangyu, FU, Jiaxi
• Granted Patent: US 10,771,056 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6257 with several inputs only combined with selecting means
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0027 Measuring means of, e.g. currents through or voltages across the switch
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Claims

1. A switch circuit, comprising:

an equalization module and a first metal-oxide-semiconductor (MOS) transistor, wherein

a gate of the first MOS transistor is connected to an output terminal of the equalization module, an input terminal of the first MOS transistor is connected to a signal source for acquiring a signal from the signal source, and an output terminal of the first MOS transistor is connected to a subsequent circuit; and

the equalization module is configured to;

supply a turning-on signal to the first MOS transistor in a case that an operation signal in response to which the switch circuit operates is acquired, to turn on the first MOS transistor; and

generate, in a case that the first MOS transistor is turned on, a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor.

2. The switch circuit according to claim 1, wherein the equalization module comprises:

a first switch, a second switch, a third switch, a first resistor, a second resistor, an equalization amplifier, and a signal detecting module, wherein

a first terminal of the first switch and a first terminal of the second switch are connected to a power supply Vdd;

a first terminal of the first resistor is connected to a second terminal of the second switch, and a second terminal of the first resistor is connected to an output terminal of the equalization amplifier;

a first terminal of the second resistor is connected to a second terminal of the first switch, and a second terminal of the second resistor is connected to a first terminal of the third switch, a first terminal of the signal detecting module, and an input terminal of the equalization amplifier;

a second terminal of the third switch is grounded;

the output terminal of the equalization amplifier serves as the output terminal of the equalization module and is connected to the gate of the first MOS transistor; and

the signal detecting module is configured to;

detect an amplitude of the signal transmitted through the first MOS transistor; and

output, from the first terminal of the signal detecting module, a signal for characterizing the amplitude of the signal transmitted through the first MOS transistor.

3. The switch circuit according to claim 2, wherein the signal detecting module comprises a second MOS transistor, wherein

a gate of the second MOS transistor serves as the first terminal of the signal detecting module, and the second MOS transistor is connected to the first MOS transistor in parallel.

4. The switch circuit according to claim 2, wherein the signal detecting module comprises a first capacitor, wherein

a first terminal of the first capacitor serves as the first terminal of the signal detecting module, and a second terminal of the first capacitor is connected to the input terminal or the output terminal of the first MOS transistor.

5. The switch circuit according to claim 2, wherein

in a case that the switch circuit is in an operation state, the first switch and the second switch are turned on, and the third switch is turned off;

and

in a case that the switch circuit is not in the operation state, the first switch and the second switch are turned off, and the third switch is turned on.

6. The switch circuit according to claim 2, wherein design parameters of the equalization module, the first MOS transistor and the first resistor are determined according to the following equation:

Gm*R0=S*Cp*R0+1+Cp/Cg

wherein Gm denotes a transconductance magnification of the equalization amplifier, R0 denotes a resistance of the first resistor, S denotes a complex frequency, Cp denotes a sum of capacitances-to-ground generated at both sides of the first MOS transistor, and Cg denotes a gate oxide capacitance generated in the first MOS transistor.

7. The switch circuit according to claim 2, wherein design parameters of the equalization module, the first MOS transistor and the first resistor are determined according to the following equation:

Gm*R0=(S*Cp*R0+1+Cp/Cg)/n

wherein Gm denotes a transconductance magnification of the equalization amplifier, R0 denotes a resistance of the first resistor, S denotes a complex frequency, Cp denotes a sum of capacitances-to-ground generated at both sides of the first MOS transistor, Cg denotes a gate oxide capacitance generated in the first MOS transistor, and n>

1.

8. The switch circuit according to claim 3, wherein a size of the first MOS transistor is greater than a size of the second MOS transistor.

9. The switch circuit according to claim 7, wherein n=3.

10. A high-speed multiplexer-demultiplexer, comprising:

at least two switch circuits, wherein each of the at least two switch circuits comprises;

an equalization module and a first metal-oxide-semiconductor (MOS) transistor, and wherein

a gate of the first MOS transistor is connected to an output terminal of the equalization module, an input terminal of the first MOS transistor is connected to a signal source for acquiring a signal from the signal source, and an output terminal of the first MOS transistor is connected to a subsequent circuit; and

the equalization module is configured to;

supply a turning-on signal to the first MOS transistor in a case that an operation signal in response to which the switch circuit operates is acquired, to turn on the first MOS transistor; and

generate, in a case that the first MOS transistor is turned on, a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor.

11. The high-speed multiplexer-demultiplexer according to claim 10, wherein the equalization module comprises:

a first switch, a second switch, a third switch, a first resistor, a second resistor, an equalization amplifier, and a signal detecting module, wherein

a first terminal of the first switch and a first terminal of the second switch are connected to a power supply Vdd;

a first terminal of the first resistor is connected to a second terminal of the second switch, and a second terminal of the first resistor is connected to an output terminal of the equalization amplifier;

a first terminal of the second resistor is connected to a second terminal of the first switch, and a second terminal of the second resistor is connected to a first terminal of the third switch, a first terminal of the signal detecting module, and an input terminal of the equalization amplifier;

a second terminal of the third switch is grounded;

the output terminal of the equalization amplifier serves as the output terminal of the equalization module and is connected to the gate of the first MOS transistor; and

the signal detecting module is configured to;

detect an amplitude of the signal transmitted through the first MOS transistor; and

output, from the first terminal of the signal detecting module, a signal for characterizing the amplitude of the signal transmitted through the first MOS transistor.

12. The high-speed multiplexer-demultiplexer according to claim 11, wherein the signal detecting module comprises a second MOS transistor, wherein

a gate of the second MOS transistor serves as the first terminal of the signal detecting module, and the second MOS transistor is connected to the first MOS transistor in parallel.

13. The high-speed multiplexer-demultiplexer according to claim 11, wherein the signal detecting module comprises a first capacitor, wherein

a first terminal of the first capacitor serves as the first terminal of the signal detecting module, and a second terminal of the first capacitor is connected to the input terminal or the output terminal of the first MOS transistor.

14. The high-speed multiplexer-demultiplexer according to claim 11, wherein

in a case that the switch circuit is in an operation state, the first switch and the second switch are turned on, and the third switch is turned off;

and

in a case that the switch circuit is not in the operation state, the first switch and the second switch are turned off, and the third switch is turned on.

15. The high-speed multiplexer-demultiplexer according to claim 11, wherein design parameters of the equalization module, the first MOS transistor and the first resistor are determined according to the following equation:

Gm*R0=S*Cp*R0+1Cp/Cg

wherein Gm denotes a transconductance magnification of the equalization amplifier, R0 denotes a resistance of the first resistor, S denotes a complex frequency, Cp denotes a sum of capacitances-to-ground generated at both sides of the first MOS transistor, and Cg denotes a gate oxide capacitance generated in the first MOS transistor.

16. The high-speed multiplexer-demultiplexer according to claim 11, wherein design parameters of the equalization module, the first MOS transistor and the first resistor are determined according to the following equation:

Gm*R0=(S*Cp*R0+1+Cp/Cg)/n

wherein Gm denotes a transconductance magnification of the equalization amplifier, R0 denotes a resistance of the first resistor, S denotes a complex frequency, Cp denotes a sum of capacitances-to-ground generated at both sides of the first MOS transistor, Cg denotes a gate oxide capacitance generated in the first MOS transistor, and n>

1.

17. The high-speed multiplexer-demultiplexer according to claim 12, wherein a size of the first MOS transistor is greater than a size of the second MOS transistor.

18. The high-speed multiplexer-demultiplexer according to claim 16, wherein n=3.