FLOATING SWITCH AND DRIVE CIRCUIT THEREOF

• US 20200136610A1
• Filed: 10/21/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Duan, Xiaoming, Chen, Jun
• Granted Patent: US 10,965,283 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance

Abstract

An apparatus can include: a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.

Claims

1. An apparatus, comprising:

a) a drive circuit for a floating switch having first and second transistors coupled in series, wherein gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together;

b) a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and

c) a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.

2. The apparatus of claim 1, wherein no current flows from the drive circuit to the source terminals of the first and second transistors due to the clamp circuit.

3. The apparatus of claim 1, wherein the clamp circuit comprises third and fourth transistors, wherein gate terminals of the third and fourth transistors are coupled together to the source terminals of the first and second transistors, such that no current flows from the drive circuit to the source terminals of the first and second transistors when the first and second transistors are turned on.

4. The apparatus of claim 3, wherein a source terminal of the third transistor is coupled to the gate terminal of the first transistor through at least one diode, and a source terminal of the fourth transistor is coupled to the gate terminal of the first transistor.

5. The apparatus of claim 3, wherein channel types of the first, second, and fourth transistors are the same, and a channel type of the third transistor is different from the channel types of the first, second, and fourth transistors.

6. The apparatus of claim 1, wherein:

a) the gate-source voltage of the first and second transistors is clamped to a first predetermined value when a logic signal is in a first state; and

b) the gate-source voltage of the first and second transistors is clamped to a second predetermined value when the logic signal is in a second state.

7. The apparatus of claim 1, wherein the control circuit comprises:

a) a first current source coupled between a pull-up power supply terminal and the gate terminal of the first transistor;

b) a second current source coupled between the gate terminal of the first transistor and a ground, wherein an output current of the second current source is greater than an output current of the first current source; and

c) a switch coupled between the first and second current sources, and being controlled to be turned on and off by a logic signal.

8. The apparatus of claim 3, wherein the clamp circuit further comprises at least one diode coupled in series between the gate terminal of the first transistor and a source terminal of the third transistor in a forward direction.

9. The apparatus of claim 6, wherein when the first and second transistors are N-channel transistors, the first predetermined value is set to maintain on states of the first and second transistors, and the second predetermined value is set to maintain off states of the first and second transistors.

10. The apparatus of claim 3, wherein when the first and second transistors are N-channel transistors, a drain terminal of the third transistor is coupled to a ground and a drain terminal of the fourth transistor is coupled to a pull-up power supply terminal.

11. The apparatus of claim 6, wherein when the first and second transistors are P-channel transistors, the first predetermined value is set to maintain the off state of the first and second transistors, and the second predetermined value is set to maintain the on state of the first and second transistors.

12. The apparatus of claim 3, wherein when the first and second transistors are P-channel transistors, a drain terminal of the third transistor is coupled to a pull-up power supply terminal and a drain terminal of the fourth transistor is coupled to a ground.

13. The apparatus of claim 1, wherein the first and second transistors are high voltage transistors.

14. The apparatus of claim 7, wherein the switch is low voltage transistor.

15. The apparatus of claim 3, wherein the third and fourth transistors are low voltage transistors.