SEMICONDUCTOR DEVICE

• US 20200136621A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: TOMITA, Takashi, FURUTA, Manabu
• Granted Patent: US 11,489,524 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: H03K 19/017509 Interface arrangements

Abstract

A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Claims

1. A semiconductor device comprising:

a pair of input terminals for receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path;

a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween;

a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

2. The semiconductor device according to claim 1,

wherein the first input signal and the second input signal represent a data value by changing to a first potential and a second potential, and represent a state control signal for controlling the semiconductor device to a predetermined state by changing to a third potential different from the first potential and the second potential,

wherein the first reception circuit generates the first output signal indicating the data value based on a comparison result of comparing in potential the first input signal with the second input signal,

wherein the second reception circuit generates the second output signal indicating whether the first input signal and the second input signal represents the state control signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

3. The semiconductor device according to claim 2,

wherein the third potential is lower than both of the first potential and the second potential,

wherein the reference potential is higher than the third potential and lower than the intermediate potential between the first potential and the second potential.

4. The semiconductor device according to claim 2,

wherein the second reception circuit includes a first comparator which compares in potential the first input signal with the reference potential;

and a second comparator which compares in potential the second input signal with the reference potential,

wherein the second reception circuit generates the second output signal based on the comparison result by the first comparator and the comparison result by the second comparator.

5. The semiconductor device according to claim 2,

wherein the second reception circuit compares in potential divided between the pair of input terminals with the reference potential, and outputs the second output signal based on a comparison result therebetween.

6. The semiconductor device according to claim 2, further comprising:

a signal input terminal for receiving data code input via a signal line different from the pair of transmission paths; and

a storage unit which stores the data code when the first input signal and the second input signal are the state control signal based on the second output signal.