Programmable Circuit Having Multiple Sectors

• US 20200136624A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 08/15/2014
• Status: Abandoned Application

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: How, Dana, Atsatt, Sean R., Hutton, Michael David, Schmit, Herman Henry
• Application Number:
  US16/726,138
• Publication Number:
  US 20200136624A1
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/007 Fail-safe circuits
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

Claims

1-20. -20. (canceled)

21. A programmable circuit comprising:

a processor subsystem;

a plurality of regions configurable to communicatively couple to the processor subsystem, wherein the plurality of regions respectively comprises;

a hard processor configurable to communicatively couple to programmable logic fabric; and

a plurality of interconnections configurable to transfer data between respective regions of the plurality of regions; and

a network-on-chip configurable to communicatively couple respective hard processors of the plurality of regions to the processor subsystem.

22. The programmable circuit of claim 21, wherein the hard processor of a respective region of the plurality of regions is configurable to execute instructions stored by a program memory associated with the respective region.

23. The programmable circuit of claim 21, wherein the network-on-chip is configurable to communicatively couple to the respective hard processors and a double data rate (DDR) memory controller.

24. The programmable circuit of claim 21, wherein the programmable circuit is configurable to perform digital signal processing.

25. The programmable circuit of claim 21, wherein a first respective hard processor of a first region of the plurality of regions is configurable to operate in parallel with a second respective hard processor of a second region of the plurality of regions.

26. The programmable circuit of claim 21, wherein at least one region of the plurality of regions performs a debug function to monitor the at least one region.

27. The programmable circuit of claim 21, wherein at least one region of the plurality of regions has a local program memory to store instructions executable by the respective hard processors.

28. A programmable logic device comprising:

a main processor;

a first region of a plurality of regions configurable to communicatively couple to the main processor, wherein the first region comprises;

a first processor configurable to communicatively couple to programmable logic; and

a first plurality of interconnections configurable to transfer data between respective regions of the plurality of regions;

a second region of the plurality of regions configurable to communicatively couple to the main processor, wherein the second region comprises;

a second processor configurable to communicatively couple to programmable logic; and

a second plurality of interconnections configurable to transfer data between respective regions of the plurality of regions; and

a network-on-chip configurable to communicatively couple the first processor and the second processor of the plurality of regions to the main processor.

29. The programmable logic device of claim 28, wherein the first or second processor is configurable to execute instructions stored by a program memory.

30. The programmable logic device of claim 28, wherein the network-on-chip is configurable to communicatively couple to the first or second processor.

31. The programmable logic device of claim 28, wherein the programmable logic device is configurable to perform digital signal processing.

32. The programmable logic device of claim 28, wherein the first processor is configurable to operate in parallel to the second processor.

33. The programmable logic device of claim 28, wherein the first processor is communicatively coupled to an address storage unit associated with the first region.

34. The programmable logic device of claim 28, wherein the network-on-chip is configurable to communicatively couple to the first processor or the second processor and a double data rate (DDR) memory controller.

35. A data processing system comprising a programmable circuit, comprising:

a first processor;

a plurality of regions comprising;

a first region of the plurality of regions is disposed horizontally adjacent to a second region of the plurality of regions and vertically adjacent to a third region of the plurality of regions;

the second region is disposed horizontally adjacent to the first region and vertically adjacent to a fourth region of the plurality of regions;

the third region is disposed horizontally adjacent to the fourth region and vertically adjacent to the first region; and

the fourth region is disposed horizontally adjacent to the third region and vertically adjacent to the second region; and

wherein the plurality of regions is configurable to communicatively couple to the first processor, wherein at least one region comprises;

a hard region processor configurable to communicatively couple to programmable logic fabric; and

a plurality of interconnections configurable to transfer data between the plurality of regions; and

a network-on-chip configurable to communicatively couple region processors of the plurality of regions to the first processor.

36. The data processing system of claim 35, wherein the hard region processor of a respective region of the plurality of regions is configurable to execute instructions stored by a program memory associated with the respective region.

37. The data processing system of claim 35, wherein the network-on-chip is configurable to communicatively couple to respective hard region processors of the plurality of regions and a double data rate (DDR) memory controller.

38. The data processing system of claim 35, wherein the data processing system is configurable to perform digital signal processing.

39. The data processing system of claim 35, wherein a first region hard processor of the first region of the plurality of regions is configurable to operate in parallel with a second region hard processor of the second region of the plurality of regions.

40. The data processing system of claim 35, wherein the at least one region of the plurality of regions performs a debug function to monitor the at least one region.